Racal Instruments 1260, Manual

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EVEN MUX Select Patterns
Hex Pattern Binary Pattern Channel Closed
00 x0xx x000 None (Control Bit = 0)
01 x0xx x001 None (Control Bit = 0)
02 x0xx x010 None (Control Bit = 0)
03 x0xx x011 None (Control Bit = 0)
04 x0xx x100 None (Control Bit = 0)
05 x0xx x101 None (Control Bit = 0)
06 x0xx x110 None (Control Bit = 0)
07 x0xx x111 None (Control Bit = 0)
40 x1xx x000 Channel 0 of EVEN MUX closed
41 x1xx x001 Channel 1 of EVEN MUX closed
42 x1xx x010 Channel 2 of EVEN MUX closed
43 x1xx x011 Channel 3 of EVEN MUX closed
44 x1xx x100 Channel 4 of EVEN MUX closed
45 x1xx x101 Channel 5 of EVEN MUX closed
46 x1xx x110 Channel 6 of EVEN MUX closed
47 x1xx x111 Channel 7 of EVEN MUX closed
ODD MUX Select Patterns
Hex Pattern Binary Pattern Channel Closed
00 0x00 0xxx None (Control Bit = 0)
08 0x00 1xxx None (Control Bit = 0)
10 0x01 0xxx None (Control Bit = 0)
18 0x01 1xxx None (Control Bit = 0)
20 0x10 0xxx None (Control Bit = 0)
28 0x10 1xxx None (Control Bit = 0)
30 0x11 0xxx None (Control Bit = 0)
38 0x11 1xxx None (Control Bit = 0)
80 1x00 0xxx Channel 0 of ODD MUX closed
88 1x00 1xxx Channel 1 of ODD MUX closed
90 1x01 0xxx Channel 2 of ODD MUX closed
98 1x01 1xxx Channel 3 of ODD MUX closed
A0 1x10 0xxx Channel 4 of ODD MUX closed
A8 1x10 1xxx Channel 5 of ODD MUX closed
B0 1x11 0xxx Channel 6 of ODD MUX closed
B8 1x11 1xxx Channel 7 of ODD MUX closed
The control registers are formed by OR-ing the EVEN control pattern with the ODD control pattern.
Example:
Control Register 0 Value = B8 hexadecimal (= 1011 1000 binary)
EVEN MUX No Channels Closed (Channels 00 through 07)
ODD MUX Channel 7 of MUX Closed (= Channel 17)
Control Register 1 Value = 40 hexadecimal (= 0100 0000 binary)
EVEN MUX Channel 0 of MUX Closed (= Channel 20)
ODD MUX No Channels Closed (Channels 30 through 37)
Control Register 2 Value = F8 hexadecimal (= 1111 1000 binary) (= B8 ORed with 40)
EVEN MUX Channel 0 of MUX Closed (= Channel 40)
ODD MUX Channel 7 of MUX Closed (= Channel 57)
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