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Rabbit 2000/3000 Microprocessor

EXX

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

H. Stack Manipulation

POP IP

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

POP IX

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

POP IY

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

POP zz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

PUSH IP

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

PUSH IX

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

PUSH IY

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

PUSH zz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

I. 16-bit Arithmetic, Logical, and Rotate

ADC HL,ss

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ADD HL,ss

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ADD IX,xx

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADD IY,yy

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADD SP,d

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AND HL,DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AND IX,DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AND IY,DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

BOOL HL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

BOOL IX

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

BOOL IY

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DEC IX

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DEC IY

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DEC ss

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

INC IX

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

INC IY

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

INC ss

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

MUL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

NEG

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

OR HL,DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

OR IX,DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

OR IY,DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

RL DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

RR DE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

RR HL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

RR IX

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

RR IY

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

SBC HL,ss

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

J. 8-bit Arithmetic and Logical

ADC A,(HL)

. . . . . . . . . . . . . . . . . . . . . . . . .13

ADC A,(IX+d)

. . . . . . . . . . . . . . . . . . . . . . .13

ADC A,(IY+d)

. . . . . . . . . . . . . . . . . . . . . . .13

ADC A,n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ADC A,r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ADD A,(HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ADD A,(IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ADD A,(IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ADD A,n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ADD A,r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AND (HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AND (IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AND (IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AND r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CP (HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CP (IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CP (IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CP n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

CP r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

NEG

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

OR (HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

OR (IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

OR (IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

OR n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

OR r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

SBC (IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

SBC (IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

SBC A,(HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

SBC A,n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

SBC A,r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

SUB (HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

SUB (IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

SUB (IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

SUB n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

SUB r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

XOR (HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

XOR (IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

XOR (IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

XOR n

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

XOR r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

K. 8-bit Bit Set, Reset, and Test

BIT b,(HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

BIT b,(IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

BIT b,(IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

BIT b,r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

RES b,(HL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

RES b,(IX+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

RES b,(IY+d)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Summary of Contents for 2000

Page 1: ...bit 2000 3000Microprocessor Instruction Reference Manual 019 0098 C 020416 This manual or an even more up to date revision is available for free download at the Rabbit website www rabbitsemiconductor...

Page 2: ...ii Rabbit 2000 3000 Microprocessor...

Page 3: ...ference Manual iii Table of Contents 1 Alphabetical Listing of Instructions 1 2 Instructions Listed by Group 3 3 Document Conventions 7 4 Processor Registers 11 5 OpCode Descriptions 13 6 Quick Refere...

Page 4: ...iv Rabbit 2000 Microprocessor...

Page 5: ...L 31 EX SP IX 31 EX SP IY 31 EXX 33 I INC IX 34 INC IY 34 INC r 34 INC ss 35 INC HL 33 INC IX d 33 INC IY d 33 IOE 36 IOI 36 IPRES 38 IPSET 0 37 IPSET 1 37 IPSET 2 37 IPSET 3 37 J JP f mn 40 JP mn 39...

Page 6: ...SH zz 76 R RA 89 RES b r 78 RES b HL 77 RES b IX d 77 RES b IY d 77 RET 79 RET f 80 RETI 81 RL DE 83 RL r 83 RL HL 82 RL IX d 82 RL IY d 82 RLA 84 RLC r 86 RLC HL 85 RLC IX d 85 RLC IY d 85 RLCA 86 RR...

Page 7: ...exed Load and Store LD HL d HL 44 LD IX d HL 45 LD IY d HL 46 LD SP n HL 48 LD SP n IX 48 LD SP n IY 48 LD HL HL d 53 LD HL IX d 53 LD HL IY d 53 LD HL SP n 54 LD IX SP n 55 LD IY SP n 57 E 16 bit Loa...

Page 8: ...R DE 88 RR HL 88 RR IX 88 RR IY 88 SBC HL ss 95 J 8 bit Arithmetic and Logical ADC A HL 13 ADC A IX d 13 ADC A IY d 13 ADC A n 14 ADC A r 14 ADD A HL 15 ADD A IX d 15 ADD A IY d 15 ADD A n 16 ADD A r...

Page 9: ...X d 87 RR IY d 87 RR r 89 RRC HL 90 RRC IX d 90 RRC IY d 90 RRC r 91 SLA HL 98 SLA IX d 98 SLA IY d 98 SLA r 99 SRA HL 100 SRA IX d 100 SRA IY d 100 SRA r 101 SRL HL 102 SRL IX d 102 SRL IY d 102 SRL...

Page 10: ...IY d 53 LD HL SP n 54 LD HL IX 54 LD HL IY 54 LD IX SP n 55 LD IX HL 56 LD IY SP n 57 LD IY HL 56 LD XPC A 61 LDP HL HL 63 LDP IX HL 63 LDP IY HL 63 LDP mn HL 64 LDP mn IX 64 LDP mn IY 64 LDP HL HL 6...

Page 11: ...enthesis are a breakdown of the total clocks The number of clocks instructions take follows a general patern There are several Rabbit instructions that do not adhere to this pattern Some instructions...

Page 12: ...on register ALTD operation is a special case Flag Description S D IOI and IOE affect destination IOI and IOE affect source S Z L V C Description Sign flag affected Sign flag not affected Zero flag aff...

Page 13: ...to PC f f condition code select 000 NZ 001 Z 010 NC 011 C 100 LZ NV 101 LO V 110 P 111 M m m the most significant bits MSB of a 16 bit constant mn mn 16 bit constant n n 8 bit constant or the least si...

Page 14: ...Carry C 0 C C 1 Carry C 1 P S 0 Minus M S 1 Positive LZ L V 0 For logic operations Logic Zero all of the four most significant bits of the result are zero NV L V 0 For arithmentic operations No Overfl...

Page 15: ...PC Index Register Index Register Stack Pointer Program Counter General Purpose External Interrupt Internal Interrupt Interrupt Priority Extension of Program Counter EIR IIR IP XPC Accumulator Flags H...

Page 16: ...12 Rabbit 2000 3000 Microprocessor...

Page 17: ...sum of the data in index register IX and a displacement value d or the sum of the data in index register IY and a displacement value d The result is then stored in the Accumulator ADC A HL ADC A IX d...

Page 18: ...data in register r any of the registers A B C D E H or L The result is stored in the Accumulator ADC A n Opcode Instruction Clocks Operation CE n ADC A n 4 2 2 A A n CF Flags ALTD I O S Z L V C F R S...

Page 19: ...displacement value d or the sum of the data in index register IY and a displacement value d The result is stored in the Accumulator ADC HL ss Opcode Instruction Clocks Operation ADC HL ss 4 2 2 HL HL...

Page 20: ...ster r any of the registers A B C D E H or L The result is stored in the Accumulator ADD A n Opcode Instruction Clocks Operation C6 n ADD A n 4 2 2 A A n Flags ALTD I O S Z L V C F R SP S D V ADD A r...

Page 21: ...data in the word register ss any of the word registers BC DE HL or SP The result is stored in HL ADD HL ss Opcode Instruction Clocks Operation 09 19 29 39 ADD HL ss ADD HL BC ADD HL DE ADD HL HL ADD H...

Page 22: ...acement d and then stored in SP This instruction is implemented for the Rabbit and is not available for the Z180 ADD IX xx ADD IY yy Opcode Instruction Clocks Operation DD 09 DD 19 DD 29 DD 39 ADD IX...

Page 23: ...This instruction is implemented for the Rabbit and is not available for the Z180 Example The instruction ALTD ADD HL DE would add the data in word register DE to the data in word register HL and store...

Page 24: ...2 of both bytes are compared etc and the associated bit in the result byte is set only if both the compared bits are set The result is stored in the Accumulator Example If the byte in the Accumulator...

Page 25: ...the word in word register DE The result is stored in IX AND IY DE performs a logical AND operation between the word in index register IY and the word in word register DE The result is stored in IY Th...

Page 26: ...the Accumulator and the byte in the register r any of the registers A B C D E H or L The relative bits of each byte are compared i e the bit 1 of both bytes are compared the bit 2 of both bytes are c...

Page 27: ...t 1 HL bit 2 HL bit 3 HL bit 4 HL bit 5 HL bit 6 HL bit 7 DD CB d 46 DD CB d 4E DD CB d 56 DD CB d 5E DD CB d 66 DD CB d 6E DD CB d 76 DD CB d 7E BIT b IX d BIT 0 IX d BIT 1 IX d BIT 2 IX d BIT 3 IX d...

Page 28: ...This instruction is implemented for the Rabbit and is not available for the Z180 BIT b r Opcode Instruction Clocks Operation b r A B C D E H L BIT b r 4 2 2 r bit CB 0 47 40 41 42 43 44 45 CB 1 4F 48...

Page 29: ...st then the low order byte The program counter is then loaded with mn 16 bit address of the first instruction of the subroutine The Stack Pointer is updated to reflect the two bytes pushed onto the st...

Page 30: ...e data HL IX d or IY d from the Accumulator If the value of the data in the Accumulator is less than the value of the data compared then the Sign Flag and the Carry Flag are set If they are equal the...

Page 31: ...ter r any of the registers A B C D E H or L This compare is accomplished by subtracting the appropriate data r from the Accumulator If the value of the data in the Accumulator is less than the value o...

Page 32: ...address is in word register HL or the data in index register IX plus a displacement value d or the data in index register IY plus a displacement value d CPL Opcode Instruction Clocks Operation 2F CPL...

Page 33: ...C D E H or L DEC IX DEC IY Opcode Instruction Clocks Operation DD 2B DEC IX 4 2 2 IX IX 1 FD 2B DEC IY 4 2 2 IY IY 1 Flags ALTD I O S Z L V C F R SP S D DEC r Opcode Instruction Clocks Operation 3D 05...

Page 34: ...0 it adds the 8 bit signed constant e to the Program Counter Two is subtracted from the value e so the instruction jumps from the current instruction and not the following instruction DEC ss Opcode I...

Page 35: ...order byte of index register IX with the data whose address is the data in the Stack Pointer register SP EX SP IY exchanges the high order byte of index register IY with the data whose address is 1 p...

Page 36: ...ernate word register DE with the data in word register HL If the ALTD instruction is present then the data in DE is exchanged with the data in the alternate word register HL The Dynamic C assembler re...

Page 37: ...m of the data in index register IX and a displacement value d or the sum of the data in index register IY and a displacement value d EXX Opcode Instruction Clocks Operation D9 EXX 2 BC BC DE DE HL HL...

Page 38: ...any of the registers A B C D E H or L INC IX INC IY Opcode Instruction Clocks Operation DD 23 INC IX 4 2 2 IX IX 1 FD 23 INC IY 4 2 2 IY IY 1 Flags ALTD I O S Z L V C F R SP S D INC r Opcode Instruct...

Page 39: ...ents the data in word register ss any of the word registers BC DE HL or SP INC ss Opcode Instruction Clocks Operation 03 13 23 33 INC ss INC BC INC DE INC HL INC SP 2 2 2 2 2 ss ss 1 BC BC 1 DE DE 1 H...

Page 40: ...ructions can be used more appropriately for external I O operations By default writes are inhibited for external I O operations and fifteen wait states are added for I O accesses WARNING If an I O pre...

Page 41: ...the contents of the register holding the previous pri orities 2 bits to the left then sets the Interrupt Priority Register bits 0 and 1 to 10 IPSET 3 The IPSET 3 instruction shifts the contents of th...

Page 42: ...nterrupt during the execution of this instruction This instruction is privileged It is implemented for the Rabbit and is not available for the Z180 Example If the Interrupt Priority register contains...

Page 43: ...ata in index register IY is loaded into the Program Counter Thus the address of the next instruction fetched is the data in IY JP mn The 16 bit constant mn is loaded into the Program Counter Thus the...

Page 44: ...set LO Logical Overflow flag is set P sign flag not set M sign flag set This instruction recognizes labels when used in the Dynamic C assembler JP f mn Opcode Instruction Clocks Operation C2 n m CA n...

Page 45: ...to the Program Counter Since the instruction takes two increments of the PC to complete two is subtracted from the displacement value so that the displacement take place from the instruction opcode T...

Page 46: ...ack the high order byte first then the low order byte Then the XPC is loaded with the 8 bit value x and the PC is loaded with the 16 bit value mn The Stack Pointer register is then updated to reflect...

Page 47: ...HL with the 8 bit con stant n LD HL r Loads the memory location whose address is the data in HL with the data in the register r any of the registers A B C D E H or L LD BC A LD DE A LD HL n LD HL r Op...

Page 48: ...nt value d Then loads the data in register H into the memory location whose address is the sum of the data in word register HL and a displacement value d plus 1 This instruction is implemented for the...

Page 49: ...index register IX and a displacement value d LD IX d r Loads the data in register r any of the registers A B C D E H or L into the memory location whose address is the sum of the data in index registe...

Page 50: ...a in index register IY and a displacement value d LD IY d r Loads the data in register r any of the registers A B C D E H or L into the memory location whose address is the sum of the data in index re...

Page 51: ...ocation whose address is 1 plus mn with the high order byte of the data in IY into LD mn ss Loads the memory location whose address is mn with the low order byte of the data in word register ss any of...

Page 52: ...Pointer SP and the displacement n Then loads the high order byte of the data in IX into the memory location whose address is the sum of data in SP the displacement n and 1 LD SP n IY Loads the low ord...

Page 53: ...address in memory is the data in word register BC or the data in word register DE or the 16 bit constant mn LD A BC LD A DE LD A mn Opcode Instruction Clocks Operation 0A LD A BC 6 2 2 2 A BC 1A LD A...

Page 54: ...Most Significant Byte MSB of the Internal Peripheral Interrupt address The value loaded in the IIR is concatenated with the appropriate Internal Peripheral address to form the 16 bit ISR starting add...

Page 55: ...nd are not available for the Z180 LD dd mn Opcode Instruction Clocks Operation ED 4B n m ED 5B n m 2A n m ED 7B n m LD dd mn LD BC mn LD DE mn LD HL mn LD SP mn 13 2 2 2 2 1 2 2 13 2 2 2 2 1 2 2 13 2...

Page 56: ...nal Interrupt Register IIR with the data in the Accumulator The IIR is used to specify the Most Significant Byte MSB of the Internal Peripheral Interrupt address The value loaded in the IIR is concate...

Page 57: ...ement d Then loads the register H with the data whose address is the data in index register IX plus a displacement d plus 1 LD HL IY d Loads the register L with the data whose address is the data in i...

Page 58: ...lable for the Z180 Description These instructions are implemented for the Rabbit and are not available for the Z180 LD HL IX Loads the word register HL with the data in index register IX LD HL IY Load...

Page 59: ...lacement n Then loads the high order byte of IX with the data whose address is the data in the Stack Pointer register plus a displacement n plus 1 This instruction is implemented for the Rabbit and is...

Page 60: ...180 LD IX mn Loads the index register IY with the 16 bit constant mn Description Loads the low order byte of index register IY with the data at the address mn and loads the high order byte of IY with...

Page 61: ...ment n Then loads the high order byte of IY with the data whose address is the data in the Stack Pointer register plus a displacement n plus 1 This instruction is implemented for the Rabbit and is not...

Page 62: ...1 2 5 2 1 2 5 2 1 2 5 2 1 2 r HL A HL B HL C HL D HL E HL H HL L HL DD 7E d DD 46 d DD 4E d DD 56 d DD 5E d DD 66 d DD 6E d LD r IX d LD A IX d LD B IX d LD C IX d LD D IX d LD E IX d LD H IX d LD L...

Page 63: ...C D E H or L with the 8 bit constant n LD r n Opcode Instruction Clocks Operation 3E n 06 n 0E n 16 n 1E n 26 n 2E n LD r n LD A n LD B n LD C n LD D n LD E n LD H n LD L n 4 2 2 4 2 2 4 2 2 4 2 2 4...

Page 64: ...other one byte register g any of the registers A B C D E H or L LD r g Opcode Instruction Clocks Operation r g A B C D E H L LD r g 2 r g A 7F 78 79 7A 7B 7C 7D B 47 40 41 42 43 44 45 C 4F 48 49 4A 4B...

Page 65: ...ension of the Program Counter XPC with the data in the Accumulator This instruction is priv ileged It is implemented for the Rabbit and is not available for the Z180 LD SP HL LD SP IX LD SP IY Opcode...

Page 66: ...d register BC is decremented and the data in word registers DE and HL are incre mented The instruction then repeats until BC equals zero If any of these block move instructions are prefixed by IOI or...

Page 67: ...then loads the follow ing 20 bit address with the data in the register H LDP IY HL Loads the memory location whose 16 least significant bits of its 20 bit address are the data in index register IY wit...

Page 68: ...location with the high order byte of index register IX LDP mn IY Loads the memory location whose 16 least significant bits of its 20 bit address are the 16 bit constant mn with the low order byte of...

Page 69: ...the register H with the data in the follow ing 20 bit address LDP HL IY Loads the register L with the data whose 16 least significant bits of its 20 bit address are the data in index register IY and t...

Page 70: ...th the data in the following 20 bit address LDP IY mn Loads the low order byte of index register IY with the data whose 16 least significant bits of its 20 bit address are the 16 bit constant mn and t...

Page 71: ...ers execution from a subroutine to the calling program by popping the Program Counter and the XPC off of the Stack in order to return from a LCALL operation The instruction first loads the low order b...

Page 72: ...If the multiplier is positive it is passed unchanged If there is a carry from this stage of the 2 s complement operation it is passed to the next stage This instruction is implemented for the Rabbit a...

Page 73: ...zero and stores the result in the Accumulator Description No operation is performed during this cycle NEG Opcode Instruction Clocks Operation ED 44 NEG 4 2 2 A 0 A Flags ALTD I O S Z L V C F R SP S D...

Page 74: ...es are compared the bit 2 of both bytes are compared etc and the associated bit in the result byte is set if either of the compared bits is set The result is stored in the Accumulator Example If the b...

Page 75: ...e data in word registers DE The result is stored in IX OR IY DE Performs a logical OR operation between the data in index register IY and the data in word register DE The result is stored in IY The re...

Page 76: ...he relative bits of each byte are compared i e the bit 1 of both bytes are compared the bit 2 of both bytes are compared etc and the associated bit in the result byte is set if either of the compared...

Page 77: ...order byte of IX with the data at the address immedi ately following the one held in SP SP is then incremented twice POP IY Loads the low order byte of index register IY with the data at the memory ad...

Page 78: ...gh order byte of zz with the data at the mem ory address immediately following the one held in SP SP is then incremented twice POP zz Opcode Instruction Clocks Operation F1 C1 D1 E1 POP zz POP AF POP...

Page 79: ...tion with the address two less than the data in SP with the low order byte of the data in IX Then SP is decremented twice PUSH IY Loads the memory location with the address 1 less than the data in th...

Page 80: ...e memory loca tion with the address two less than the data in SP with the low order byte of the data in zz Then SP is decre mented twice PUSH zz Opcode Instruction Clocks Operation F5 C5 D5 E5 PUSH zz...

Page 81: ...t 4 HL HL bit 5 HL HL bit 6 HL HL bit 7 DD CB d 86 DD CB d 8E DD CB d 96 DD CB d 9E DD CB d A6 DD CB d AE DD CB d B6 DD CB d BE RES b IX d RES bit 0 IX d RES bit 1 IX d RES bit 2 IX d RES bit 3 IX d R...

Page 82: ...by performing a logical AND between the selected bit and its complement RES b r Opcode Instruction Clocks Operation b r A B C D E H L RES b r 4 2 2 r r bit CB 0 87 80 81 82 83 84 85 CB 1 8F 88 89 8A...

Page 83: ...rogram Counter PC with the data at the memory address in the Stack Pointer SP then loads the high order byte of PC with the data at the memory address immediately following the one held in SP The data...

Page 84: ...t set Z zero flag set NC carry flag not set C carry flag set LZ NV Logic Zero Overflow flag is not set LO V Logic Zero Overflow flag is set P sign flag not set M sign flag set RET f Opcode Instruction...

Page 85: ...s 1 higher than the data in SP and loads the high order byte of the PC with the data whose address is two higher than the data in the SP The data in the SP is then incremented three times This privile...

Page 86: ...es to bit 0 and bit 7 moves to the CF See Figure 1 below Example If the HL contains 0x4545 the byte in the memory location 0x4545 is 0110 1010 and the CF is set then after the execution of the operati...

Page 87: ...contents of the register r any of the register A B C D E H or L Each bit in the register moves to the next highest order bit position bit 0 moves to bit 1 etc while the CF moves to bit 0 and bit 7 mo...

Page 88: ...ontents of the Accumulator Each bit in the register moves to the next highest order bit position bit 0 moves to bit 1 etc while the CF moves to bit 0 and bit 7 moves to the CF See Figure 1 on page 82...

Page 89: ...e Figure 2 below Example If the HL contains 0x4545 the byte in the memory location 0x4545 is 0110 1010 and the CF is set then after the execution of the operation RLC HL the byte in memory location 0x...

Page 90: ...highest order bit position bit 0 moves to bit 1 etc while bit 7 moves to both bit 0 and the CF See Figure 2 on page 85 RLC r Opcode Instruction Clocks Operation CB 07 CB 00 CB 01 CB 02 CB 03 CB 04 CB...

Page 91: ...ister IY and a displacement d Bit 0 moves to the CF bits 1 through 7 move to the next lowest order bit position and the CF moves to bit 7 See Figure 3 below RR HL RR IX d RR IY d Opcode Instruction Cl...

Page 92: ...the right with the Carry Flag CF the data in index register IX or IY Bit 0 moves to the CF bits 1 through 15 move to the next lowest order bit position and the CF moves to bit 15 See Figure 3 on page...

Page 93: ...data in the Accumulator Bit 0 moves to the CF bits 1 through 7 move to the next lowest order bit position and the CF moves to bit 7 See Figure 3 on page 87 RR r Opcode Instruction Clocks Operation CB...

Page 94: ...gister moves to the next lowest order bit position bit 7 moves to bit 6 etc while bit 0 moves to both bit 7 and the CF See Figure 4 below RRC HL RRC IX d RRC IY d Opcode Instruction Clocks Operation C...

Page 95: ...lowest order bit position bit 7 moves to bit 6 etc while bit 0 moves to both bit 7 and the CF See Figure 4 on page 90 RRC r Opcode Instruction Clocks Operation CB 0F CB 08 CB 09 CB 0A CB 0B CB 0C CB...

Page 96: ...first loading the high order byte of the PC into the memory location with the address 1 less than the number in the Stack Pointer SP Then the low order byte of the PC is loaded into the memory locati...

Page 97: ...mulator The result is stored in the Accumulator These operations output an inverted carry The Carry Flag is set if the Accumulator is less than the data being subtracted from it The Carry Flag is clea...

Page 98: ...tor These operations output an inverted carry The Carry Flag is set if the Accumulator is less than the data being subtracted from it The Carry Flag is cleared if the Accumulator is greater than the d...

Page 99: ...n the data being subtracted from it The Carry Flag is cleared if the Accumulator is greater than the data being subtracted from it Description Sets the Carry Flag CF SBC HL ss Opcode Instruction Clock...

Page 100: ...CB d C6 DD CB d CE DD CB d D6 DD CB d DE DD CB d E6 DD CB d EE DD CB d F6 DD CB d FE SET b IX d SET bit 0 IX d SET bit 1 IX d SET bit 2 IX d SET bit 3 IX d SET bit 4 IX d SET bit 5 IX d SET bit 6 IX d...

Page 101: ...C D E H or L SET b r Opcode Instruction Clocks Operation SET b r 4 2 2 r r bit b r A B C D E H L CB 0 C7 C0 C1 C2 C3 C4 C5 CB 1 CF C8 C9 CA CB CC CD CB 2 D7 D0 D1 D2 D3 D4 D5 CB 3 DF D8 D9 DA DB DC DD...

Page 102: ...hrough 6 are each shifted to the next highest order bit position bit 0 moves to bit 1 etc Bit 7 is shifted to the Carry Flag CF Bit 0 is reset See Figure 5 below SLA HL SLA IX d SLA IY d Opcode Instru...

Page 103: ...c Bit 7 is shifted to the Carry Flag CF Bit 0 is reset See Figure 5 on page 98 SLA r Opcode Instruction Clocks Operation CB 27 CB 20 CB 21 CB 22 CB 23 CB 24 CB 25 SLA r SLA A SLA B SLA C SLA D SLA E S...

Page 104: ...shifted to the next lowest order bit position bit 7 is shifted to bit 6 etc Bit 7 is also cop ied to itself Bit 0 is shifted to the Carry Flag CF See Figure 6 below SRA HL SRA IX d SRA IY d Opcode Ins...

Page 105: ...so copied to itself Bit 0 is shifted to the Carry Flag CF See Figure 6 on page 100 SRA r Opcode Instruction Clocks Operation CB 2F CB 28 CB 29 CB 2A CB 2B CB 2C CB 2D SRA r SRA A SRA B SRA C SRA D SRA...

Page 106: ...Each bit is shifted to the next lowest order bit position Bit 7 shifts to bit 6 etc Bit 0 shift to the Carry Flag CF Bit 7 is reset See Figure 7 below SRL HL SRL IX d SRL IY d Opcode Instruction Clock...

Page 107: ...it 0 shift to the Carry Flag CF Bit 7 is reset See Figure 7 on page 102 SRL r Opcode Instruction Clocks Operation CB 3F CB 38 CB 39 CB 3A CB 3B CB 3C CB 3D SRL r SRL A SRL B SRL C SRL D SRL E SRL H SR...

Page 108: ...cement d The result is stored in the Accumulator Description Subtracts from the data in the Accumulator the 8 bit constant n The result is stored in the Accumulator SUB HL SUB IX d SUB IY d Opcode Ins...

Page 109: ...register r any of the registers A B C D E H or L The result is stored in the Accumulator SUB r Opcode Instruction Clocks Operation 97 90 91 92 93 94 95 SUB r SUB A SUB B SUB C SUB D SUB E SUB H SUB L...

Page 110: ...compared etc and the associated bit in the result byte is set if and only if one of the two compared bits is set The result is stored in the Accumulator Example If the HL contains 0x4000 and the memo...

Page 111: ...lator and the register r any of the regis ters A B C D E H or L The corresponding bits of each byte are compared i e the bit 1 of both bytes are compared the bit 2 of both bytes are compared etc and t...

Page 112: ...108 Rabbit 2000 3000 Microprocessor...

Page 113: ...truction set by the Rabbit 2000 3000 An M indicates that this instruction is from the Z180 but has been modified A P indicates a privileged instruction Instruction Opcode byte 1 Opcode byte 2 Opcode b...

Page 114: ...01 d 12 2 2 2 1 2 3 f b V IY d IY d 1 DEC IX 11011101 00101011 4 2 2 IX IX 1 DEC IY 11111101 00101011 4 2 2 IY IY 1 DEC r 00 r 101 2 fr V r r 1 DEC ss 00ss1011 2 r ss ss 1 DJNZ e 00010000 e 2 5 2 2 1...

Page 115: ...0100010 n m 15 2 2 2 2 1 3 3 d mn IXL mn 1 IXH LD mn IY 11111101 00100010 n m 15 2 2 2 2 1 3 3 d mn IYL mn 1 IYH LD mn ss 11101101 01ss0011 n m 15 2 2 2 2 1 3 3 d mn ssl mn 1 ssh LD SP n HL 11010100 n...

Page 116: ...C 1 DE DE 1 HL HL 1 LDIR 11101101 10110000 6 7i 2 2 1 2 3 2 i 1 d repeat DE HL BC BC 1 DE DE 1 HL HL 1 until BC 0 LDP HL HL 11101101 01100100 12 2 2 2 3 3 HL L HL 1 H Addr 19 16 A 3 0 N LDP IX HL 1101...

Page 117: ...2 1 2 2 1 PCL SP PCH SP 1 SP SP 2 RET f 11 f 000 2 8 2 1 2 2 1 if f PCL SP PCH SP 1 SP SP 2 RETI 11101101 01001101 12 2 2 1 2 2 2 1 IP SP PCL SP 1 PCH SP 2 SP SP 3 NP RL HL 11001011 00010110 10 2 2 1...

Page 118: ...6 0 0 CY IX d 7 SLA IY d 11111101 11001011 d 00100110 13 2 2 2 2 2 3 f b L IY d IY d 6 0 0 CY IY d 7 SLA r 11001011 00100 r 4 2 2 fr L r r 6 0 0 CY r 7 SRA HL 11001011 00101110 10 2 2 1 2 3 f b L HL H...

Page 119: ...ustomer and Rabbit Semiconductor prior to use Life support devices or systems are devices or systems intended for surgical implantation into the body or to sustain life and whose failure to perform wh...

Page 120: ...ii Rabbit 2000 3000 Microprocessor...

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