R.V.R. ELETTRONICA S.r.l. (BO)
Pag. 16
PTRLNV/2/S3 and PTRL-NV/2/HP/S3 - Technical and Maintenance Manual
allows the L and R signals to be separated from the multiplexed signal,
plus the suppression of the 38 KHz frequency.
The level of the left and right signals is set by the corresponding
selector situated on the front panel. The signals are then filtered at
15 KHz and pre-emphasized (50 uS CCIR, 75 uS FCC) before being sent to
the multiplex circuit.
The audio signals from the two SCA inputs are mixed in to provide the
output.
In mixer mode (Mono MPX) the stereo encoder is bypassed, the right input
accepts a mono signal and the left input accepts a multiplex signal upto
100 KHz. The SCA inputs remain unchanged.
Three rectifiers allow the peak levels of the two inputs "LEFT/MPX" and
"RIGHT/MONO" to be displayed on the analog meter, and provide the audio
detector circuit with the deviation level.
2.5 MAIN CARD
The
Main
card
is
situated
on
the
lower
left
side
of
the
unit
(Photo 1). This card contains a voltage-controlled oscillator (VCO),
housed in a metal box, which generates the operating frequency of the
transmitter which has been programmed. The audio signal, coming from the
two MONO and STEREO connectors on the front panel, is amplified and
injected into the VCO to produce a class F3E modulation. On the PLL circuit
the VCO operating frequency is divided down and compared to a reference
frequency, generated by a 4 MHz quartz crystal which is thermally-
compensated by a PTC. The error voltage is filtered and fed-back to
guarantee the stability of the VCO frequency. An indicator on the front
panel lights when the circuit is not locked.
2.4 R.F. POWER AMPLIFIER
The power stage is mounted on a heatsink to dissapate generatde heat,
and totally enclosed in a metal screening box (Photo 1-2). This sub-
assembly is mounted to the base of the chassis in a contral position.
The R.F. signal coming from the VCO, at power level of about 10mW, passes
through the driver stage (BFR96) and is amplified by the final stage
(BFQ34 and BFQ68) upto a level of 2 W (versions are available with 5 W
and 10 W power outputs). The signal then passes through a low-pass filter
to remove any harmonic components. A directional coupler allows both
direct and reflected power to be measured and fed-back to the power
supply. The direct power reading is also connected to the multimeter.
2.6 CPU
The CPU is housed in a metal box and mounted centrally on the rear
of
the
front
panel
(Photo
1-2).
This
circuit
converts
the
number
corresponding to the selected operating frequency into binary code which
is written to the programmable dividers of the PLL. This allows the VCO
to lock to the desired operating frequency. Several of the transmitter's
Summary of Contents for PTRL-NV/2/S3
Page 141: ...PTRL NV 2 S3 PTRL NV 2 HP S3 PSSW PTNV 1 6 Appendice Tecnica Rev 0 1 15 05 02...
Page 148: ...PTRL NV 2 S3 PTRL NV 2 HP S3 2 10 CPU NV Technical Appendix Rev 0 1 12 09 02...
Page 151: ...PTRL NV 2 S3 PTRL NV 2 HP S3 CPU NV 5 10 Appendice Tecnica Rev 0 1 12 09 02...
Page 157: ...PTRL NV 2 S3 PTRL NV 2 HP S3 CSSDC30A003 1 6 Technical Appendix Rev 0 1 06 09 02...
