UMTS/HSPA Module Series
UG96 Hardware Design
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Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name
Pin No. I/O
Description
Comment
PCM_CLK
4
DO
PCM data bit clock
1.8V power domain
PCM_SYNC
5
DO
PCM data frame
synchronization signal
1.8V power domain
PCM_IN
6
DI
PCM data input
1.8V power domain
PCM_OUT
7
DO
PCM data output
1.8V power domain
I2C_SCL
40
OD
I2C serial clock
Require external pull-up resistor.
I2C_SDA
41
OD
I2C serial data
Require external pull-up resistor.
CLK_OUT
25
DO
Clock output
Provide a digital clock output for
an external audio codec.
If unused, keep it open.
In PCM audio format, the MSB of the channel included in the frame (PCM_SYNC) is clocked on the
second CLK rising edge after the PCM_SYNC pulse rising edge. The period of the PCM_SYNC signal
(frame) lasts for data word bit +1 clock pulses.
UG96
’s firmware has integrated the configurations on NAU8814 /ALC5616/MAX9860 application with I2C
interface.
AT+QDAC
command is used to configure the external codec chip linked with PCM interface,
and refer to
document [1]
for more details. Data bit is 32 bit and the sampling rate is 8KHz. The following
figure shows the timing of the application with ALC5616 codec.
PCM_CLK
PCM_SYNC
PCM_IN/OUT
32
1
0
31
Sampling freq.=8KHz
32-bit data word
BCLK=264KHz
33
MSB
Figure 27: PCM Master Mode Timing
In general, the BitClockFrequency (BCLK) is calculated by the following expression:
BitClockFrequency=(Data1) × SamplingFrequency
