UMTS/HSPA Module Series
UC20 Hardware Design
UC20_Hardware_Design Confidential / Released 38 / 82
RTS
65
DI
Request to send.
1.8V power domain.
DTR
66
DI
Data terminal ready.
1.8V power domain.
TXD
67
DO
Transmit data.
1.8V power domain.
RXD
68
DI
Receive data.
1.8V power domain.
Table 10: Pin Definition of the Debug UART Interface
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
12
DO
Transmit data.
1.8V power domain.
DBG_RXD
11
DI
Receive data.
1.8V power domain.
The logic levels are described in the following table.
Table 11: Logic Levels of Digital I/O
Parameter
Min
Max
Unit
V
IL
-0.3
0.6
V
V
IH
1.2
2.0
V
V
OL
0
0.45
V
V
OH
1.35
1.8
V
UC20 provides 1.8V UART interface. A level translator should be used if your application is equipped with
a 3.3V UART interface. A level translator TXS0108PWR provided by
Texas Instrument
is recommended.
The following figure shows the reference design.
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