Smart Module Series
SC206E_Series_Hardware_Design 61 / 115
3.20.1. MIPI Design Considerations
⚫
Special attention should be paid to the pin definition of LCM and camera connectors. Make sure the
module and the connectors are correctly connected.
⚫
MIPI lines are high-speed signal lines for DSI-supported maximum data rate of up to 1.5 Gbps and
CSI-supported maximum data rate of up to 2.5 Gbps. The differential impedance should be
controlled to 1
00 Ω. Additionally, it is recommended to route the trace on the inner layer of PCB, and
do not cross it with other traces. For the same group of DSI or CSI signals, keep all the MIPI traces
of the same length. In order to avoid crosstalk, keep a distance of 1.5 times the trace width among
MIPI signal lines. During impedance matching, do not connect GND on different planes to ensure
impedance consistency.
⚫
It is recommended to select a low-capacitance TVS for ESD protection and the recommended
parasitic capacitance should be below 1 pF.
⚫
Route MIPI traces according to the following rules:
a) The total trace length should not exceed 240 mm;
b) Control the differential impedance to 10
0 Ω ± 10 %;
c) Control intra-lane length difference within 0.7 mm;
d) Control inter-lane length difference within 1.4 mm.
Table 24: MIPI Trace Length Inside the Module
Pin Name
Pin No.
Length (mm)
Length Difference (P - N)
DSI_CLK_N
52
38.53
0.23
DSI_CLK_P
53
38.30
DSI_LN0_N
54
38.59
0.16
DSI_LN0_P
55
38.43
DSI_LN1_N
56
38.22
-0.25
DSI_LN1_P
57
38.47
DSI_LN2_N
58
38.84
0.28
DSI_LN2_P
59
38.56
DSI_LN3_N
60
38.74
0.26
DSI_LN3_P
61
38.48
CSI1_CLK_N
63
18.87
-0.03
CSI1_CLK_P
64
18.84
CSI1_LN0_N
65
19.42
0.24
