Smart Module Series
SC206E_Series_Hardware_Design 60 / 115
The following is a reference circuit design for 3-camera applications.
c
a
m
e
ra
0
c
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CAM0_PWDN
CAM0_MCLK
CAM0_I2C_SDA
CAM0_I2C_SCL
_
CSI0_LN3_P
CSI0_LN3_N
CSI0_LN2_P
CSI0_LN2_N
CSI0_LN1_P
CSI0_LN1_N
CSI0_LN0_P
CSI0_LN0_N
CAM1_ RST
CAM1_ PWDN
CAM1_ MCLK
CSI1_LN3_P
CSI1_LN3_N
CSI1_LN2_P
CSI1_LN2_N
CSI1_LN1_P
CSI1_LN1_N
CSI1_LN0_P
CSI1_LN0_N
CSI0_ CLK_P
CSI0_ CLK_N
CSI1_ CLK_P
CSI1_ CLK_N
LDO15A_1V8
2
.2
K
2
.2
K
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1
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n
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1
μF
4.7
μF
4
.7
μ
F
1
μ
F
1
μ
F
4
.7
μ
F
CAM0_ RST
CAM2_PWDN
CAM2_MCLK
CAM1_I2C_SDA
_
CAM1_I2C_SCL
CAM2_RST
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2
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AVDD
DVDD
DOVDD
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
1
μF
2.2K
2.2K
DVDD
EMI
EMI
4.7
1
μF
μF
AVDD
DOVDD
OUT
GND
IN
EN
LDO
VPH_PWR
1
μF
AF_VDD
OUT
GND
IN
EN
LDO
VPH_PWR
GPIO
1
μF
VDD_2V8
GPIO
OUT
GND
IN
EN
LDO
1
μF
GPIO
VPH_PWR
Figure 22: Reference Circuit Design for 3-Camera Applications
In 3-camera applications, CSI1_LN3_P and CSI1_LN3_N are used as MIPI clock signals of camera 2.
CSI1_LN2_P and CSI1_LN2_N are used as MIPI data signals of camera 2.
NOTE
