5G Module Series
RM510Q-GL Hardware Design
RM510Q-GL_Hardware_Design 45 / 88
T
FCPO#-CLKREQ#
> 90 ms
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_REFCLK
T
power-on
T
turn-on
VCC
RESET_N
Module power-on or insertion detection
FCPO#
RFFE_VIO_1V8
System turn-on and booting
V
IH
≥ 1.19 V
1.5 V
3.7 V
1.8 V
T
FCPO#-PERST#
> 100 ms
T
PERST#-CLK
> 100 us
Figure 21: PCIe Power-up Timing of the Module
Table 18: PCIe Power-up Timing of Module
4.4. PCM Interface
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 19: Pin Definition of PCM Interface
Symbol
Min.
Typ.
Max.
Comment
T
power-on
0m s
20 ms
-
System power-on time.
It is depend on host device.
T
turn-on
-
68 ms
-
System turn-on time
T
FCPO#-CLKREQ#
90 ms
100 ms
-
Power valid to CLKREQ# output active
T
FCPO#-PERST#
100 ms -
-
Power valid to PERST# input inactive
T
PERST#-CLK
100
μs -
-
REFCLK stable before PERST# inactive
Pin No. Pin Name
I/O
Description
DC Characteristics
20
PCM_CLK
DI, PD
PCM data bit clock
1.8 V
22
PCM_DIN
DI, PD
PCM data input
1.8 V
24
PCM_DOUT
DO, PD
PCM data output
1.8 V
28
PCM_SYNC
DI,PD
PCM data frame sync
1.8 V
