LTE-A Module Series
EM06 Series Hardware Design
EM06_Series_Hardware_Design 36 / 69
The following table shows the pin definition of PCM and I2C interfaces which can be applied to audio
codec design.
Table 11: Pin Definition of PCM and I2C Interfaces
The clock and mode can be configured by AT command, and the default configuration is the master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [2]
for details about
AT+QDAI
command.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Module
1.8 V
4
.7
K
BCLK
LRCK
DAC
ADC
SCL
SDA
B
IA
S
MICBIAS
INP
INN
LOUTP
LOUTN
Codec
4
.7
K
Figure 21: Reference Design of PCM Application with Audio Codec
Pin Name
Pin No.
I/O
Description
Comment
PCM_IN
22
DI
PCM data input
1.8 V power domain.
PCM_OUT
24
DO
PCM data output
1.8 V power domain.
PCM_SYNC
28
IO
PCM data frame
synchronization signal
1.8 V power domain.
PCM_CLK
20
IO
PCM data bit clock
1.8 V power domain.
In the master mode, it serves as
an output signal.
In the slave mode, it serves as
an input signal.
If unused, keep it open.
I2C_SCL
58
DO
I2C serial clock
Used for external codec.
Need to be pulled up to 1.8 V.
I2C_SDA
56
IO
I2C serial data
