Quectel EM05, Hardware Design

Page: 17 / 60

LTE Module Series
EM05 Hardware Design
EM05_Hardware_Design Confidential / Released 16 / 59
7 USB_D+ USB_DP IO USB differential data bus (+)
8 W_DISABLE1# W_DISABLE1# DI
Airplane mode control. Active
low.
1.8/3.3V.
9 USB_D- USB_DM IO USB differential data bus (-)
10 GPIO_9 LED# OD
It is an open drain and active low
signal. Requires a pull up
resistor on the host.
It is used to indicate the RF
status of the module.
If unused,
keep it open.
11 GND GND Ground
12 Key Notch Notch
13 Key Notch Notch
14 Key Notch Notch
15 Key Notch Notch
16 Key Notch Notch
17 Key Notch Notch
18 Key Notch Notch
19 Key Notch Notch
20
GPIO_5
(AUDIO_0)
PCM_CLK IO
PCM clock. In master mode, it is
an output signal. In slave mode,
it is an input signal.
If unused, keep it open.
1.8V
21 CONFIG_0 CONFIG_0
Unconnected internally.
EM05 is configured as
WWAN-SSIC-0.
22
GPIO_6
(AUDIO_1)
PCM_IN DI PCM data input 1.8V
23
GPIO_11
(WAKE_ON_
WWAN#)
WOWWAN# OD
A signal to wake up the host.
It is open drain and active low.
Requires a pull up resistor on
the host.
If unused,
keep it open.
24
GPIO_7
(AUDIO_2)
PCM_OUT DO PCM data output 1.8V
25 DPR DPR* DI
Body specific absorption rate
(SAR) detection
1.8V
26
GPIO_10
W_DISABLE2#
W_DISABLE2#* DI
GPS control
Active low
1.8V
27 GND GND Ground
Quectel
Confidential