Quectel EG21-G, Hardware Design

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LTE Module Series
EG21-G Hardware Design
EG21-G_Hardware_Design 25 / 100
VDD_SDIO 34
PO
SD card SDIO bus
pull-up power
I
O
max=50mA
1.8V/2.85V
configurable.
Cannot be used for
SD card power.
If unused, keep it
open.
BT UART Interface*
BT_RTS* 37 DI
BT UART request to
send
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
If unused, keep it
open.
BT_TXD* 38 DO
BT UART transmit
data V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
If unused, keep it
open.
BT_RXD* 39 DI
BT UART receive
data
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
If unused, keep it
open.
BT_CTS* 40 DO
BT UART clear to
send V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
Cannot be pulled up
before startup.
If unused, keep it
open.
BT_EN* 139 DO
BT function control
via FC20 module V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
If unused, keep it
open.
RF Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
ANT_DIV 35 AI Diversity antenna 50Ω impedance
If unused, keep it
open.
ANT_MAIN 49 IO Main antenna 50Ω impedance
ANT_GNSS 47 AI GNSS antenna 50Ω impedance
If unused, keep it
open.
GPIO Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
WAKEUP_IN 1 DI Sleep mode control
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
Cannot be pulled up
before startup.
Low level wakes up