LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
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Figure 19: Main UART Reference Design (Translator Chip)
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Another example with transistor circuit is shown as below. For the design of circuits shown in dotted lines,
see that of circuits in solid lines, but pay attention to the direction of connection.
Figure 20: Main UART Reference Design (Transistor Circuit)
1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps.
2. The main UART interface of the module should be disconnected in PSM and power off modes.
Otherwise, the module will have additional power consumption and may have damaged pins.
3. It is recommended to use a level-shifting chip without internal pull-up, such as TXB0108PWR, for
voltage level translation.
NOTE
