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8.2.3 Device Control Register (Base + 2)
The Device Control Register is written to control the parallel port control
signals, to enable the interrupt, and to set the data direction control bit.
This bit is inverted an output onto the STROBE output.
This bit controls the strobe signal.
strobe
*0
This bit is inverted and output onto the AUTOFEED output.
'1' = Printer will generate a line feed after each line is printed.
'0' = No automatic line feed will occur.
autofd
*1
This bit is output onto the INIT output.
This bit controls the initialize signal.
nInit
*2
This bit is inverted and output onto the SELECTIN output.
'1' = Selects the printer.
'0' = Printer is not selected.
SelectIn
*3
Interrupt Request Enable Bit.
'1' = A system interrupt is generated by a positive going ACK
input.
'0' = Interrupt is disabled.
ackIntEn
4
Controls the direction of the data port in bi-directional and EPP
modes. This bit is write only. This bit is ignored in the standard
(unidirectional) parallel port mode.
'1' = To read data port in EPP and bi-directional modes.
'0' = To configure the parallel port for output mode.
Direction
5
Always reads a 0
-
6
Always reads a 0
-
7
Description
Name
Bit
Figure 18. Data Control Register Table
* NOTE:
The control lines represented by these bits have open collector
drivers in the standard mode. In the bi-directional and EPP modes, they
have active pull-ups (TTL compatible).
8.2.4 EPP Address Register (Base + 3)
This register is only available in the EPP mode. Writing this register
initiates an EPP Address Write Cycle. Reading this register initiates an
EPP Address Read Cycle.
8-4
Quatech Inc.
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