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Bit 1:

RXSRC --- Receive FIFO DMA Source:

This

bit determines which SCC pins are used to control transmit and receive DMA
transactions between the SCC and the external FIFOs (when enabled). The
transmit data FIFO is always used with SCC channel A. The receive data FIFO
may be used with SCC channel A by setting RXSRC to logic 0, or with SCC
channel B by setting RXSRC to logic 1. (See page 23 for information on using
channel B.)

W/REQA

DTR/REQA

Transmit

DMA

W/REQB

W/REQA

Receive DMA

RXSRC = 1

RXSRC = 0

Bit 0:

Reserved, always 0.

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Summary of Contents for MPAP-200

Page 1: ...0 RS 422 485 PCMCIA SYNCHRONOUS ADAPTER for PCMCIA Card Standard compatible machines User s Manual QUATECH INC TEL 330 655 9000 5675 Hudson Industrial Parkway FAX 330 655 9010 Hudson Ohio 44236 www quatech com ...

Page 2: ...product to which it refers at any time and without notice The authors have taken due care in the preparation of this document and every attempt has been made to ensure its accuracy and completeness In no event willQuatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented in this document or any softwa...

Page 3: ... has been made to guarantee the accuracy of this manual Quatech Inc assumes no liability for damages resulting from errors in this document Quatech Inc reserves the right to edit or append to this document at any time without notice Please complete the following information and retain for your records Have this information available when requesting warranty service DATE OF PURCHASE MODEL NUMBER MP...

Page 4: ...5 Installing OS 2 PCMCIA Support 25 5 4 Monitoring The Status Of PCMCIA Cards 25 5 3 OS 2 Client Driver Configuration Examples 24 5 2 3 Hot Swapping 24 5 2 2 Auto Fallback configuration 24 5 2 1 Tying a configuration to a particular socket 23 5 2 OS 2 Client Driver Installation 23 5 1 System Requirements 23 5 OS 2 Software Installation 22 4 3 Configuration Options 18 4 Windows 95 98 Installation 1...

Page 5: ...18 Receive FIFO Timeout Register 53 17 Receive Pattern Count Register 52 16 Receive Pattern Character Register 51 15 FIFO Control Register 50 14 FIFO Status Register 49 13 Interrupt Status Register 47 12 Configuration Register 45 11 Communications Register 44 10 7 Receive FIFO timeout 43 10 6 Receive pattern detection 42 10 5 Accessing the SCC while FIFOs are enabled 42 10 4 4 Controlling the FIFO...

Page 6: ...63 22 3 3 Bad Parameters 62 22 3 2 Insufficient Number Of Command Line Arguments 62 22 3 1 Resources Not Available ...

Page 7: ...t oriented synchronous protocols such as HDLC and SDLC The SCC also offers internal functions such as on chip baud rate generators and digital phase lock loop DPLL for recovering data clocking from received data streams Because the PCMCIA 2 1 standard does not include a direct memory access DMA interface the MPAP 200 300 supports only interrupt driven communications To compensate for the lack of D...

Page 8: ...r DOS it is also possible to use the Quatech MPAP 200 enabler program Software installation and configuration is covered in other chapters of this manual 3 Attach the narrow connector on the supplied cable to the socket on the end of the MPAP 200 The connector is keyed so that it can only be inserted in one orientation The connector should attach firmly and smoothly Do not force the connector into...

Page 9: ...e required no yes Automatic configuration of MPAP 200 upon insertion Hot Swapping socket controller Intel 82365 or compatible only PCMCIA card and Socket Services socket independent Interfaces to DOS executable DOS device driver File type MPAP2EN EXE MPAP2CL SYS File name Enabler Client Driver Table 1 Client driver versus enabler for DOS Windows 3 x IMPORTANT Do not use both the client driver and ...

Page 10: ...0 client driver accepts between zero and eight sets of desired configurations from the user on the command line When an MPAP 200 is inserted desired configurations are tried in the order they appear on the command line from left to right If the user does not provide any desired configurations the client driver will ask Card Services to automatically determine a configuration for the card Each desi...

Page 11: ...er If a card is present in a socket at boot time the card s configuration is reported on the screen as the client driver loads This feature can be used to verify the changes just made to the CONFIG SYS file 7 If the Client Driver reports the desired configuration the installation process is complete and the MPAP 200 may be removed from the system if desired 8 If configuration of the card fails the...

Page 12: ...f 300 hex and IRQ 5 If address 300 hex or IRQ 5 is unavailable attempt to configure the card with a base address assigned by Card Services and IRQ 10 If IRQ 10 is also unavailable attempt to configure the card with a base address and an IRQ assigned by Card and Socket Services DEVICE C MPAP 200 MPAP2CL SYS b300 i5 i10 Example Attempt to configure an MPAP 200 inserted into socket 0 with a base addr...

Page 13: ...If more than one MPAP 200 is installed in a system the enabler must be executed separately for each card A card that is removed and reinserted must be reconfigured by executing the enabler again 3 3 2 DOS Enabler Installation To install the DOS enabler program copy the file MPAP2EN EXE from the MPAP 200 distribution diskette onto the system s hard drive No setup steps are required IMPORTANT The en...

Page 14: ...uired when configuring a card B The base I O address of the MPAP 200 This number must be a three digit hexadecimal value ending in 0 This parameter is always required when configuring a card I The interrupt level IRQ of the MPAP 200 This decimal number must be one of the following values 3 4 5 7 9 10 11 12 14 15 or 0 if no IRQ is desired This parameter is always required when configuring a card W ...

Page 15: ... this MPAP1EN S R W S The PCMCIA socket into which the MPAP 200 will be inserted This value is a decimal number ranging from 0 to 15 This parameter is always required when releasing a card s configuration R Release the resources previously allocated to the MPAP 200 This parameter is always required when releasing a card s configuration This option must not be used when configuring an MPAP 200 W op...

Page 16: ...00 in socket 1 with a base address of 300H and IRQ 3 using a configuration memory window at segment D800 MPAP2EN EXE s1 b300 i3 wd8 Example Release the configuration used by the MPAP 200 in socket 0 MPAP2EN EXE s0 r Example Release the configuration used by the MPAP 200 in socket 1 using a configuration memory window at segment CC00 MPAP2EN EXE s1 r wcc 16 ...

Page 17: ...NF file to determine the system resources required by the MPAP 200 searches for available resources to fill the boards requirements and then updates the hardware registry with an entry that allocates these resources The Syncdrive DLL and VxD can then be used to access the card 4 1 Using the Add New Hardware Wizard The following instructions provide step by step instructions on installing the MPAP ...

Page 18: ...ice Click the Next button to continue 3 On the next dialog select the CD ROM drive checkbox Insert the Quatech COM CD shipped with the card into the CD drive Click the Next button 4 Windows should locate the INF file on the CD and display a dialog that looks like this Click the Next button 18 ...

Page 19: ...5 Windows will copy the INF file from the CD and display a final dialog indicating that the process is complete Click the Finish button 19 ...

Page 20: ...his lists all hardware devices registered inside the Windows registry Additional information is available on any of these devices by click on the device name and then selecting the Properties button 3 Double click the device group Synchronous_Communication The MPAP 200 model name should appear in the list of adapters 4 Double click the MPAP 200 model name and a properties box should open for the h...

Page 21: ...on should be used to avoid creating device conflicts with other hardware in the system 4 3 Configuration Options If the Use Automatic Settings box is unchecked various options can be enabled by selecting a different basic configuration in the Setting based on drop down box Revision B5 hardware and later only 0000 Factory default Suggested for nearly all customers 0001 Reserved DO NOT USE 0002 Memo...

Page 22: ...he card The client driver will attempt to configure an MPAP 200 with the first available configuration listed from left to right on the command line Each desired configuration must be enclosed in parentheses and must be separated from other desired configurations by a space on the command line Within each desired configuration the parameters are separated using commas no spaces 1 Copy the MPAP200 ...

Page 23: ...parenthesis where X is the desired socket number 5 2 2 Auto Fallback configuration OS 2 Card Services is capable of automatically determining a configuration for a PCMCIA device but due to limitations in Quatech s Syncdrive driver software the client driver does not support this feature This support is planned for a future release of both the client driver and Syncdrive 5 2 3 Hot Swapping The clie...

Page 24: ... 2 configure it at base address 110 hex and IRQ 15 If any of these resources are not available the card will not be configured Up to two MPAP 200s can be used DEVICE C MPAP 200 MPAP200 SYS 300 5 S1 110 15 S2 5 4 Monitoring The Status Of PCMCIA Cards OS 2 Warp provides a utility called Plug and Play for PCMCIA that can be used to monitor the status of each PCMCIA socket In OS 2 2 1 this utility is ...

Page 25: ... Full PCMCIA support is built into OS 2 Warp 3 0 and later On OS 2 2 1 and 2 11 PCMCIA Card Services is built in but you must add Socket Services separately The necessary files can be found onCompuserve in the OS2SUPPORT forum library 23 in the file OS2PCM ZIP and may be available elsewhere Quatech does not distribute these files 25 ...

Page 26: ... MPAP 200 with the settings expected by the Syncdrive application before the application tries to use the card Under Windows 95 98 the card is automatically configured To find the settings click the right mouse button on the My Computer icon and select Properties Select the Device Manager tab and double click the card s entry under the Synchronous Communication section Select the Resources tab to ...

Page 27: ... space is reserved for future use The MPAP 200 address map is shown in Table 2 Reserved Base F Reserved Base E Receive FIFO Timeout Register Base D Receive Pattern Count Register Base C Receive Pattern Character Register Base B FIFO Control Register Base A FIFO Status Register Base 9 Interrupt Status Register Base 8 Reserved Base 7 Reserved Base 6 Configuration Register Base 5 Communications Regis...

Page 28: ...dge by reading Read Register 2 in channel B of the SCC The value read can also be used to vector to the appropriate part of the ISR 4 Service the SCC interrupt by reading the receiver buffer writing to the transmit buffer issuing commands to the SCC etc 5 Write a Reset Highest Interrupt Under Service IUS command to the SCC by writing 0x38 to Write Register 0 6 Check for other interrupts pending in...

Page 29: ...neration and checking Automatic zero insertion and deletion Automatic flag insertion between messages Address field recognition I field residue handling CRC generation and detection SDLC loop mode with EOP recognition loop entry and exit Byte oriented Synchronous Communications Internal external character synchronization 1 or 2 sync characters in separate registers Automatic Cyclic Redundancy Chec...

Page 30: ...rt The only exception to this rule is when accessing the transmit and receive data buffers These registers can be accessed with the two step process described or with a single read or write to the data port The following examples illustrate how to access the internal registers of the SCC Table 3 on page 20 describes the read registers and Table 4 on page 21 describes the write registers for each c...

Page 31: ...thout interrupts by reading the status of RR0 and then reading or writing data to the SCC buffers via CPU port accesses Interrupts on the SCC can be sourced from the receiver the transmitter or External Status conditions At the event of an interrupt Status can be determined then data can be written to or read from the SCC via CPU port accesses Further information on this subject is found on page 1...

Page 32: ... HDLC Enhancement Register WR7 Sync character 2nd byte or SDLC Flag WR7 Sync character 1st byte or SDLC address field WR6 Transmitter initialization and control WR5 Transmit Receive miscellaneous parameters and codes clock rate stop bits parity WR4 Receiver initialization and control WR3 Interrupt vector WR2 Interrupt control Wait DMA request control WR1 Command Register Register Pointer CRC initi...

Page 33: ...Mode 1 16 32 or 64 Baud_Rate desired baud rate for Clock_Frequency 9 8304 MHz 3FFE hex 16382 300 1FFE hex 8190 600 0FFE hex 4094 1200 07FE hex 2046 2400 03FE hex 1022 4800 01FE hex 510 9600 00FE hex 254 19200 007E hex 126 38400 Time Constant Baud Rate Table 5 time constants for common baud rates 9 3 SCC Data Encoding Methods The SCC provides four different data encoding methods selected by bits 6 ...

Page 34: ...lied to TRXCA and RTXCA from the cable The W REQB signal is used to generate DMA requests between the SCC and the external FIFOs if channel B is used for receive 9 4 2 Extra clock support for channel A The TRXCB clock output can be routed back to RTXCA as another way to use the channel B baud rate generator to derive an independent clock for the channel A receiver This is controlled by the RCKEN b...

Page 35: ...l work Write Control Port A set pointer bits for desired register Read or Write Control Port A read or write desired channel A register Write Control Port B set pointer bits for desired register Read or Write Control Port B read or write desired channel B register The following sequences will NOT work Write Control Port A set pointer bits for desired register Read or Write Control Port B read or w...

Page 36: ...e enabled they are accessed through either the channel A or channel B SCC Data Port address Writing to Base 0 or Base 2 will cause a byte to be written into the transmit FIFO Reading from Base 0 or Base 2 will cause a byte to be read from the receive FIFO The FIFOs cannot be accessed if they are disabled If the FIFOs are disabled reads or writes of the SCC Data Ports access the receive or transmit...

Page 37: ...arious SCC registers need to be set in a specific manner as shown on the following pages Because the data transfer between the FIFOs and the SCC is controlled entirely by hardware per character transmit and receive interrupts should be disabled Interrupts on transmit underruns and or special receive conditions should usually be enabled so that end of frame conditions can be detected IMPORTANT The ...

Page 38: ...for W REQA timing 1 4 Assert transmit DMA request when entry location of internal FIFO is empty 0 5 WR7A Enable WR7A 1 0 WR15A Enable DMA request on transmit on DTR REQA 1 2 WR14A Disable transmit interrupts 0 1 Enable receive interrupts on special conditions only recommended or disable them completely 11 or 00 4 3 Use W REQA for receive 1 5 Set W REQA for DMA Request mode 1 6 Enable DMA request o...

Page 39: ...recommended or disable them completely 11 or 00 4 3 Use W REQB for receive 1 5 Set W REQB for DMA Request mode 1 6 Enable DMA request on W REQB This bit should be set after the other bits in WR1 are set as desired 1 7 WR1B Assert transmit DMA request when entry location of internal FIFO is empty 0 5 WR7A Enable WR7A 1 0 WR15A Disable DMA request on transmit on DTR REQA 0 2 WR14A Disable transmit i...

Page 40: ...C See Table 10 on page 36 for details Software can read data from the receive FIFO as desired RX_PAT bit 3 Special receive pattern detected Software can read bytes from the receive FIFO until the FIFO is empty Receive data timeout with non empty FIFO Software can read at least 512 bytes from the receive FIFO RX_FIFO bit 2 Receive FIFO filled past the half full mark Software can write at least 512 ...

Page 41: ... see Table 13 on page 40 10 5 Accessing the SCC while FIFOs are enabled The SCC channel A and channel B control port registers are always accessible regardless of whether the external FIFOs are enabled or disabled While the FIFOs are enabled SCC data port accesses are redirected to the FIFOs Access to the SCC s transmit or receive registers while the FIFOs are enabled is possible indirectly by usi...

Page 42: ...8 is set For instance the MPAP 200 can watch for the end of text character to be received or for three consecutive pad characters to be received For byte synchronous operation with simple unique markers in the data stream this feature may be quite useful Even if it is not however the MPAP 200 can certainly be operated with per character interrupts enabled and the external FIFOs disabled The tradeo...

Page 43: ...d a receive FIFO interrupt is generated and RX_FIFO bit in the Interrupt Status Register see page38 is set A character time is approximated by counting eight ticks of the bit clock To use this feature the receive clock must be output on TRXCA It can come from either an external source or from the channel A baud rate generator While the RTXCA signal is typically used for a receive clock it is not c...

Page 44: ...YNC External Sync Enable If this bit is set logic 1 software controlled sync is disabled and the SCC s SYNCA input is driven by the signal coming on pin 21 of the DB 25 connector If this bit is clear logic 0 the SW_SYNC bit can be used to drive SYNCA Bit 5 Reserved always 0 Bit 4 SW_SYNC Software Sync On This bit is used to drive the active low SYNC input of the channel A receiver The SYNC signal ...

Page 45: ...nerated by the TRxC pin on channel A of the SCC and to be transmitted on pins 24 and 11 of the DB 25 connector When cleared logic 0 the DTE receives TCLK on pins 15 and 12 of the DB 25 connector Bit 1 RXDEN Enable Receivers When set logic 1 this bit enables the RS 422 485 receivers for data and handshake signals When cleared logic 0 the receivers are disabled Bit 0 TXDEN Enable Transmitters When s...

Page 46: ...es products that are not equipped with external data FIFOs will return 0 in this bit location Bit 6 Reserved always 0 Bits 5 4 INTS1 INTS0 Interrupt Source and Enable Bits These two bits determine the source of interrupts The only valid source is interrupt from the SCC INTSCC Below is the mapping for these bits Note that FIFO related interrupts will occur only when INTSCC is chosen reserved 1 1 IN...

Page 47: ...ernal FIFOs when enabled The transmit data FIFO is always used with SCC channel A The receive data FIFO may be used with SCC channel A by setting RXSRC to logic 0 or with SCC channel B by setting RXSRC to logic 1 See page 23 for information on using channel B W REQA DTR REQA Transmit DMA W REQB W REQA Receive DMA RXSRC 1 RXSRC 0 Bit 0 Reserved always 0 47 ...

Page 48: ...es in the received data stream where n is the value set in the Receive Pattern Count Register This bit is set logic 1 to indicate the interrupt It remains set until cleared by writing a 1 to this bit Bit 2 RX_FIFO Receive FIFO Interrupt The receive FIFO interrupt occurs when the number of bytes held in the external receive FIFO rises above the half full mark or when a receive FIFOtimeout occurs Th...

Page 49: ...eceive FIFO is completely full The FIFO will accept no more data from the SCC Bit 5 RXH Receive FIFO Half Full This bit is set logic 1 while the external receive FIFO is at least half full Bit 4 RXE Receive FIFO Empty This bit is set logic 1 when the external receive FIFO is completely empty Bit 3 Reserved always 0 Bit 2 TXF Transmit FIFO Full This bit is set logic 1 when the external transmit FIF...

Page 50: ...ttern detection circuitry Clear this bit logic 0 to disable pattern detection See page 32 for details on the receive pattern detection feature Bit 5 EN_TO Enable Receive Timeout Set this bit logic 1 to enable the external receive FIFO timeout Clear this bit logic 0 to disable the receive FIFO timeout See page 33 for details on the receive FIFO timeout feature Bit 4 RX_RESET Reset Receive FIFO Set ...

Page 51: ...r is Base B hex This register can be ignored if the external FIFOs are not being used character value 0 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 14 Receive Pattern Character Register Read Write Bits 7 0 Receive Pattern Character This is the numeric value of the character to be detected See page 32 for details on the receive character pattern detection feature 51 ...

Page 52: ...ing used counter value 0 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 15 Receive Pattern Count Register Read Write Bits 7 0 Receive Pattern Count This value is the number of times that the character stored in the Receive Pattern Character Register see page 41 must be consecutively detected for the receive character pattern detect interrupt to be generated See page 32 for details on th...

Page 53: ...6 Receive FIFO Timeout Register Read Write Bit 7 X16_MODE Clock Mode If this bit is set logic 1 the data clock is divided by 16 prescaled before it is fed to the timeout circuitry This is useful for asynchronous operation If this bit is clear logic 0 the data clock is not prescaled Bit 6 Reserved always 0 Bits 5 0 Timeout Interval This is the number of character times that must elapse before a non...

Page 54: ...el B The SCC has no actual DSR inputs The transmit clock TCLK SCC TRxCA pin can be transmitted on TTCLK or received on RTCLK depending on TCKEN The receive clock RCLK SCC RTxC pins can be received on RRCLK or can be generated using the TRxCB pin depending on RCKEN The receive clock cannot be transmitted TCLK and RCLK can also be internally sourced from the channel A baud rate generator Figure 1 sh...

Page 55: ...iver so a 5 volt signal on pin 21 will assert SYNCA a 5 volt signal will deassert SYNCA The SCC must be specifically programmed to recognize external synchronization 19 2 MPA 200 and EIA 530 Compatibility The MPAP 200 is designed to be functionally compatible with Quatech s MPA 200 DTE adapter for the ISA bus The MPAP 200 connector pinout varies slightly from that of the MPA 200 with the local and...

Page 56: ...DB RTCLK X 15 TxDA pin BA TXD X 14 CTSA pin CB CTS X 13 TRxCA pin DB RTCLK X 12 TRxCA pin DA TTCLK X 11 DCDA pin CF CD X 10 RTxC pins DD RRCLK X 9 DCDA pin CF CD X 8 AB DGND 7 DCDB pin CC DSR X 6 CTSA pin CB CTS X 5 RTSA pin CA RTS X 4 RxDA pin BB RXD X 3 TxDA pin BA TXD X 2 CGND 1 SCC Pin or Register Bit Circuit Signal From DTE To DTE Pin Table 17 Connector Pin Definitions 19 3 Null modem cables ...

Page 57: ...received from a remote DTE data station to the DTE CIRCUIT CA REQUEST TO SEND CONNECTOR NOTATION RTS RTS DIRECTION To DCE This signal controls the data channel transmit function of the local DCE and on a half duplex channel the direction of the data transmission of the local DCE CIRCUIT CB CLEAR TO SEND CONNECTOR NOTATION CTS CTS DIRECTION From DCE This signal indicates to the DTE whether the DCE ...

Page 58: ...LK DIRECTION To DCE This signal generated by the DTE provides the DCE with element timing information pertaining to the data transmitted by the DTE The DCE can use this information for its received data CIRCUIT DB TRANSMIT Signal ELEMENT TIMING DCE Source CONNECTOR NOTATION RTCLK RTCLK DIRECTION From DCE This signal generated by the DCE provides the DTE with element timing information pertaining t...

Page 59: ...D 25 connector Transmit drivers RS 422 485 compatible 5 Mbps typical maximum data rate Receive buffers RS 422 485 compatible 5 Mbps typical maximum data rate I O Address range Sixteen byte contiguous range required determined by PCMCIA system Interrupt levels One IRQ required determined by PCMCIA system DMA channels Not supported by PCMCIA 2 1 bus Power requirements 100 mA at 5 volts typical 59 ...

Page 60: ...nction of the Card and Socket Services software is to track which system resources memory addresses I O addresses IRQs etc are available for assignment to inserted PCMCIA cards Occasionally Card Services may incorrectly determine that a particular resource is free when it is actually in use or vice versa Most DOS based Card and Socket Services generate a resource table in a file typically in the f...

Page 61: ...e system this region of DOS memory must be excluded from the memory manager s control Consult the documentation provided with the memory manager software for instructions on how to exclude this memory region Some systems use the high memory area for BIOS shadowing to improve overall system performance In order for the enabler to operate BIOS shadowing must be disabled in the address range specifie...

Page 62: ... base address or IRQ value may be out of range Make sure that the base address is a hexadecimal number between 100 hex and 3F0 hex ending in 0 Make sure that the IRQ is a decimal number between 2 and 15 62 ...

Page 63: ...56 ...

Page 64: ...MPAP 200 User s Manual Revision 2 32 March 2004 P N 940 0129 232 57 ...

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