LIST OF FIGURES
Figure 1.
Default address and IRQ settings
2
Figure 2.
Diagram of QS-100M / ES-100M
3
Figure 3.
Port address map
5
Figure 4.
Examination of a serial port base address
6
Figure 5.
Serial port base I/O address selection switches
7
Figure 6.
Interrupt level (IRQ) selection
8
Figure 7.
Enabling the Interrupt Status Register
9
Figure 8.
Interrupt Status Register contents
9
Figure 9.
Use of DTEs and DCEs in a communications link
10
Figure 10.
Cabling requirements for RS-232-C devices
10
Figure 11.
QS-100M / ES-100M connector definitions
11
Figure 12.
QS-100M / ES-100M output connectors
11
Figure 13.
Auxiliary signal configuration jumpers
12
Figure 14.
Output connector configuration
13
Figure 15.
Serial port register address map for 16450/16550
15
Figure 16.
Interrupt Enable Register bit definitions
16
Figure 17.
Interrupt Identification Register bit definitions
17
Figure 18.
Interrupt Identification Register bit decoding
17
Figure 19.
16550 FIFO Control Register bit definitions
18
Figure 20.
Line Control Register bit definitions
19
Figure 21.
Modem Control Register bit definitions
20
Figure 22.
Line Status Register bit definitions
21
Figure 23.
Modem Status Register bit definitions
22
Figure 24.
Input clock frequency options
25
Figure 25.
Divisor latch settings for common baud rates
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