Quatech DSCLP-200 User Manual Download

Page: 46 / 48

9 Specifications

Bus interface:

PCI, 32-bit bus, Universal Voltage Signaling
IBM-compatible computers

Dimensions:

approx. 4.725" x 2.5"

Serial ports

Controller:

16550 with 16-byte FIFOs

(16550 with 64-byte FIFOs optional)

Interface:

DSCLP: one male D-25 connector
(Two female D-9 connectors
using adapter cable)
SSCLP: one female D-9 connector

Transceivers:

MAX-3076E or compatible

Differential output:

2V min. with 50-ohm load (RS-422)
1.5V min. with 27-ohm load (RS-485)

Output rise/fall time:

3ns min., 40ns max., 15ns typ.

Differential input
threshold:

-0.2V min., +0.2V max.

Input resistance:

12k ohm min., 15k ohm typ.

Input current:

+/- 1.0mA max.

Power requirements

+5 volts:

approx. 320 mA

Temperature

operating 0° to 70°
storage -50° to 80°

Humidity:

10% to 90%

DSCLP/SSCLP-200/300 User's Manual

Summary of Contents for DSCLP-200

Page 1: ... Two and One Channel RS 422 485 Low Profile Asynchronous Communications Adapter for PCI bus User s Manual QUATECH INC TEL 330 655 9000 5675 Hudson Industrial Parkway FAX 330 655 9010 Hudson Ohio 44236 http www quatech com ...

Page 2: ...y period Any damage that results from improper installation operation or general misuse voids all warranty rights Please complete the following information and retain for your records Have this information available when requesting warranty service DATE OF PURCHASE MODEL NUMBER DSCLP 200 300 or SSCLP 200 300 PRODUCT DESCRIPTION DSCLP Two Channel RS 422 485 Asynchronous PCI Bus Communications Adapt...

Page 3: ... to ensure its accuracy and completeness In no event will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented in this document or any software programs that might accompany this document Quatech Inc encourages feedback about this document Please send any written comments to the Technical Support...

Page 4: ... EEC Standards to which Conformity is Declared EN50081 1 EN55022 EN60555 2 EN60555 3 EN50082 1 IEC 801 2 IEC 801 3 IEC 801 4 Type of Equipment Information Technology Equipment Equipment Class Commercial Residential Light Industrial Product Name PCI Two Port or One Port Serial Communications Card Model Number DSCLP 200 300 SSCLP 200 300 DSCLP SSCLP 200 300 User s Manual iv ...

Page 5: ...e Special Registers 16 4 1 Base Address and Interrupt Level IRQ 16 4 Address Map and Special Registers 15 3 Hardware Installation 13 2 4 2 Force High Speed UART Clock X2 X4 or X8 J3 4 5 13 2 4 1 Enable Scratchpad Register SPAD J2 13 2 4 Clock Rate and Optional Registers 12 2 3 5 RXEN0_SEL RXEN1_SEL J16 23 12 2 3 4 TGL0_SEL1 0 TGL1_SEL1 0 J15 14 22 21 12 2 3 3 RCLK0_SEL RCLK1_SEL J13 20 12 2 3 2 AU...

Page 6: ...ection 43 7 6 Termination Resistors 41 7 5 Half Duplex Full Duplex Auto Toggle Selection 40 7 4 AUXIN AUXOUT Loopback 40 7 3 TCLK 39 7 2 RCLK 39 7 1 RTS cts Handshake 38 7 External Connections 36 6 2 1 QTPCI EXE 35 6 2 DOS and other operating systems 35 6 1 OS 2 vi DSCLP SSCLP 200 300 User s Manual ...

Page 7: ...DSCLP SSCLP 200 300 User s Manual 7 ...

Page 8: ...e configuration The card is automatically configured by the computer s BIOS or operating system The two serial ports share a single interrupt line and are addressed in a contiguous block of 16 bytes A special interrupt status register is provided to help software to manage the shared interrupt The DSCLP 200 300 s serial ports are implemented using 16550 Universal Asynchronous Receiver Transmitters...

Page 9: ...full or half duplex operation Jumpers J10 J22 grouped together at the end of the board opposite the D type connector D 25 for DSCLP D 9 for SSCLP control special options Any changes from the factory default should be made before installing the DSCLP 200 300 in the computer These settings can also be changed in Device Manager under Windows operating systems 2 1 RS 422 or RS 485 Signal Line Terminat...

Page 10: ...section 7 2 3 Full duplex Half duplex Operation The DTR or RTS modem control output of the UART can be used to enable and disable the transmit drivers The inverse of these signals can also be used to enable and disable the receivers These options are selectable per channel The factory default as shown in Figure 2 is for both the drivers and receivers of both channels to be continuously enabled Two...

Page 11: ...TS0_SEL AUX0_SEL0 AUX0_SEL1 J10 J11 J12 RCLK0_SEL TGL0_SEL0 TGL0_SEL1 J13 J14 J15 RXEN0_SEL CTS1_SEL AUX1_SEL0 J16 J17 J18 AUX1_SEL1 RCLK1_SEL TGL1_SEL0 J19 J20 J21 TGL1_SEL1 RXEN1_SEL J22 J23 SPAD J2 Figure 2 Right Card Edge Jumpers DSCLP SSCLP 200 300 User s Manual 11 ...

Page 12: ...J13 or J20 the mode selection is RCLK TCLK With Jumpers installed on J13 or J20 the mode selection is RCLK AUXIN 2 3 4 TGL0_SEL1 0 TGL1_SEL1 0 J15 14 22 21 With NO jumpers on J15 14 or J22 21 the mode selection is TXEN 1 With Jumpers installed on J14 or J21 and NO jumpers on J15 or J22 the mode selection is TXEN DTR With Jumpers installed on J15 or J22 and NO jumpers on J14 or J21 the mode selecti...

Page 13: ... the Interrupt Status Register and the Options Register are not available X8 X4 X2 J3 J4 J5 J2 SPAD Figure 4 Enable scratchpad registers 2 4 2 Force High Speed UART Clock X2 X4 or X8 J3 4 5 These jumpers force an increase of the UART input clock frequency by a factor of two four or eight This feature can allow legacy software to use baud rates above 115 200 bits per second It is also useful if the...

Page 14: ...tions Register powerup default is for a standard times 1 clock of 1 8432 MHz for compatibility with standard serial ports Figure 5 Clock multiplier jumper options X8 X4 X2 J3 J4 J5 J2 SPAD factory default X8 X4 X2 J3 J4 J5 J2 SPAD X8 mode X8 X4 X2 J3 J4 J5 J2 SPAD X4 mode X8 X4 X2 J3 J4 J5 J2 SPAD X2 mode DSCLP SSCLP 200 300 User s Manual 14 ...

Page 15: ...ing the Option Retaining Bracket ORB screw 5 Replace the system cover according to the instructions provided by the computer manufacturer 6 Attach and secure the cable connectors to the desired equipment 7 Turn on the power of the computer system The output of the DSCLP 200 300 is a 25 pin D connector A cable is provided to convert the D 25 into two standard female D 9 connectors Please see sectio...

Page 16: ... bytes as shown in Figure 7 Base Address 8 to Base Address 15 Port 2 Base Address 0 to Base Address 7 Port 1 I O Address Range Channel Figure 7 Port Address Map All serial ports share the same IRQ The DSCLP 200 300 signals a hardware interrupt when any port requires service The interrupt signal is maintained until no port requires service Interrupts are level sensitive on the PCI bus The base addr...

Page 17: ... removed 1 Interrupt Status Register removed 0 Register selected for address 7 accesses SPAD Jumper DLAB Bit Figure 8 DLAB bit selects between special registers 4 3 Interrupt Status Register The read only Interrupt Status Register can be used to quickly identify which serial ports require servicing after an interrupt Reading the Interrupt Status Register will return the interrupt status of the ent...

Page 18: ...e access to the QMCR The QMCR of the entire DSCLP 200 300 is shown in Figure 9a 00 TXEN Auto 01 TXEN DTR 10 TXEN RTS 11 TXEN TOGGLES DURING X MIT 1 0 0 AUXOUT RTS 1 AUXOUT TCLK 2 0 RCLK TCLK CTS AUXIN 1 RCLK AUXIN CTS RTS 3 0 Bits 2 and 3 are used 1 RCLK TCLK CTS RTS AUXOUT AUXIN 4 0 RXEN 1 1 RXEN TXEN 5 0 always 0 6 0 always 0 7 MSB Description Bit Figure 9a Quatech Modem Control Register DSCLP S...

Page 19: ...on The ID bits are used to identify the DSCLP 200 300 as a Quatech Enhanced Serial Adapter Logic operations are performed such that the values read back from these bits will not necessarily be the values that were written to them Bit ID1 will return the logical AND of the values written to ID 1 0 while bit ID0 will return their exclusive OR Software can thus identify a Quatech Enhanced Serial Adap...

Page 20: ...always return the clock rate multiplier at which the board is operating 921 6 kbaud 14 7456 MHz X8 1 1 460 8 kbaud 7 3728 MHz X4 0 1 230 4 kbaud 3 6864 MHz X2 1 0 115 2 kbaud 1 8432 MHz X1 default 0 0 Maximum Data Rate UART Clock Frequency Clock Rate Multiplier RR0 RR1 Figure 12 Rate Register bit definition At powerup and reset the Options Register is initialized to 0 The DSCLP 200 300 will thus p...

Page 21: ...n Select Search for the best driver for your device Check the Removable media and Specify location box Click the Next button 2 Window will locate the proper INF file and copy the file from the CD Click the Next button 3 The final dialog screen will verify the file copy from theCD Click the Finish button DSCLP SSCLP 200 300 User s Manual 21 ...

Page 22: ...ialog box insert the Quatech COM CD shipped with the device Click the OK button 3 The following dialog box will display the appropriate INF file from the CD in the drive Click the OK button 4 Window will copy the INF file from the CD and display a final dialog indication that the process is complete Click the Finish button DSCLP SSCLP 200 300 User s Manual 22 ...

Page 23: ...l appear at start up Click the Next button 2 Select Search for the best driver for you device Click the Next button 3 On the next dialog select the CD ROM DRIVE check box Insert the Quatech COM CD shipped with the device into the CD ROM drive Click the Next button DSCLP SSCLP 200 300 User s Manual 23 ...

Page 24: ...propriate INF file on the diskette in the drive Click the Next button 5 Window will copy the INF file from the diskette and display a final dialog indication that the process is complete Click the Finish button DSCLP SSCLP 200 300 User s Manual 24 ...

Page 25: ...l appear If you have never installed a Quatech PCI communications adapter before the dialog box may simply indicate that it has found a PCI Card 2 Select the radio button for Driver from disk provided by hardware manufacturer Click the OK button to continue 3 An Install From Disk dialog box should pop up Insert the diskette with the Quatech INF files on it select the correct drive letter and click...

Page 26: ...ip button and the files will not be installed This is all right if the latest version of these drivers are currently in the WINDOWS SYSTEM directory 9 The New Hardware Found dialog will repeat for each of the serial ports on the DSCLP 200 300 as each port is registered with Windows 95 10 Installation is complete 5 5 Windows NT The Windows NT device driver is installed by running the SETUP program ...

Page 27: ...ice Manager Consult Windows on line help for details on the use of the Device Manager The following instructions provide step by step instructions on viewing resources used by the DSCLP 200 300 in Windows using the Device Manager utility Select Start Help from within Windows for additional information on this utility 1 Double click the System icon inside the Control Panel folder This opens up the ...

Page 28: ...ecause PCI is a true plug and play bus do not attempt to modify the configuration values listed Click Cancel to exit without making changes 6 Double click the hardware class Ports Com and LPT Each Quatech PCI Serial Port listed in this class is a child device of the DSCLP 200 300 parent device Windows 95 does not assign COM1 COM4 to ports addressed at nonstandard locations So in Windows 95 the DSC...

Page 29: ...s the ports UART compatibility mode and FIFO threshold levels to be configured The threshold values of full scale for the transmit buffer and scale for the receive buffer are optimal for most applications Note that the FIFO option for each of the DSCLP 200 300 s two ports is configured independently 9 Use the Logical COM Port names to access the serial ports on your DSCLP 200 300 through your soft...

Page 30: ... to this hardware class The full device name for the DSCLP 200 300 is Quatech DSCLP 200 300 Two Port RS 422 485 Serial Adapter 4 Open the Properties dialog for the DSCLP 200 300 device then click the Resources tab to view the Input Output Range and Interrupt Request resource allocations 5 Open the Properties dialog for the DSCLP 200 300 device then click the Advanced tab to view the clock rate set...

Page 31: ...lways be double the rate requested by the applications This mode is useful for legacy applicattions which cannot request baud rates over 115 200 230 400 X2 The X1 clock mode mimics a standard COM port The hardware drivers lock the clock to the standard rate The port will run at the baud rate requested by the application 115 200 X1 Auto clock mode enables applications to request any baud rate up to...

Page 32: ...ave and use this feature Clocks RTS routed to AUXOUT AUXIN routed to CTS and TCLK routed to RCLK Used when RTS CTS handshaking is required Modem Control RTS routed to CTS AUXIN routed to AUXOUT and TCLK routed to RCLK Used when external handshaking or clocking signals are not available Loopback All RS 422 485 Connector Setup DSCLP SSCLP 200 300 User s Manual 32 ...

Page 33: ...what you transmit sometimes called echo Always Receive Receive Control 8 To summarize the RS 422 485 output drivers enable options The DSCLP 200 300 s ports may be configured for either full duplex or half duplex operation with this option The default setting is the RS 422 485 ports are configured for full duplex operation with the RS 422 485 output drivers always enabled In half duplex mode the R...

Page 34: ...he transmit buffer and scale for the receive buffer are optimal for most applications Note that the FIFO option for each of the DSCLP 200 300 s two ports is configured independently DSCLP SSCLP 200 300 User s Manual 34 ...

Page 35: ...e which is to use the DSCLP 200 300 must be able to accommodate any valid assignments of these resources For Windows 95 Windows NT and OS 2 the Quatech device drivers determine what the resource assignments are and proceed accordingly In other cases however the user must intervene The discussion below will center on DOS but the concepts can be applied to other operating systems as well Many DOS ap...

Page 36: ...s been pressed In this example the DSCLP 200 300 uses I O base address FFA0 hex and IRQ 3 The hardware revision of the DSCLP 200 300 is also displayed Pressing the N key will show similar information for all non Quatech PCI devices in the system including those devices integrated on the motherboard The QTPCI program is capable only of displaying the PCI configuration It cannot be used to make chan...

Page 37: ...egions etc Pressing the N key will show similar information for all non Quatech PCI devices in the system including those devices integrated on the motherboard In this example the Base addr 0 resource is reserved For users interested in even more details PCI BIOS information can be displayed by pressing the B key Pressing the I key displays thePCI interrupt routing table Figure 14 QTPCI EXE Expert...

Page 38: ...ected one of the UART s signals either DTR or RTS is used to enable the transmitter drivers The inverse of the transmitter enable can be used to enable the receiver drivers Factory installed resistors allow for signal line termination in compliance with the RS 422 and RS 485 standards The desired termination can be selected or removed per port by applying a jumper Configuration is done using jumpe...

Page 39: ...t RTS on AUXOUT Receive CTS on AUXIN Loopback RTS to CTS Jumpers J10 12 CTS0_SEL AUX0_SEL0 AUX0_SEL1 J10 J11 J12 CTS0_SEL AUX0_SEL0 AUX0_SEL1 J10 J11 J12 Figure 16 RTS CTS selection 7 2 RCLK This is the clock signal used by the receiver portion of the UART It is generally provided by connecting it to the UART s own transmit clock output TCLK This is done by not connecting pins 1 and 2 of the jumpe...

Page 40: ...J13 RCLK0_SEL J13 AUX0_SEL0 AUX0_SEL1 J11 J12 Figure 18 TCLK selection 7 4 AUXIN AUXOUT Loopback The AUXIN signal is an input from the external device and connecting it to the AUXOUT signal provides for a loopback mode of operation In other words whatever signal is transmitted by the external device over the AUXIN line will be fed back to the external device over the AUXOUT line This mode is accom...

Page 41: ...ble If a jumper is applied between pins 1 and 2 of jumper block J16 the receivers for RxD and AUXIN will be disabled when the transmit drivers are enabled and vice versa based on the DTR or RTS connections on pins 1 2 of J14 and J15 To operate in half duplex DTR mode apply jumpers between pins 1 and 2 of jumper blocks J14 and J16 To operate in half duplex RTS mode apply jumpers between pins 1 and ...

Page 42: ...14 16 TGL0_SEL0 TGL0_SEL1 J14 J15 RXEN0_SEL J16 TGL0_SEL0 TGL0_SEL1 J14 J15 RXEN0_SEL J16 TGL0_SEL0 TGL0_SEL1 J14 J15 RXEN0_SEL J16 Auto Toggle Operation TGL0_SEL0 TGL0_SEL1 J14 J15 RXEN0_SEL J16 Figure 20 Half full duplex and Auto Toggle selection DSCLP SSCLP 200 300 User s Manual 42 ...

Page 43: ...emoved for individual signal lines using jumper blocks J6 J9 RS 422 Rt 100 ohm 1 2W RS 485 Rt 120 ohm 1 2W RS 422 485 Receiver Rt RXD AUXIN RXD AUXIN or RS 485 termination 120 omhs RS 422 termination 100 ohms factory default no termination Jumpers J6 J9 1 3 4 2 1 3 4 2 1 3 4 2 Figure 21 RS 422 485 Line termination resistance values DSCLP SSCLP 200 300 User s Manual 43 ...

Page 44: ...le D 9 connectors The SSCLP 200 300 has a single D 9 connector The serial port connector definitions are listed in Figure 22 3 GND 9 AUXIN 5 AUXIN 6 AUXOUT 1 AUXOUT 8 RxD 4 RxD 7 TxD 2 TxD D 9 Connector Pin SignalDescription Figure 22 DSCLP 200 300 connector definitions 1 2 3 4 5 6 7 8 9 D 9 connector Figure 23 DSCLP 200 300 output connectors DSCLP SSCLP 200 300 User s Manual 44 ...

Page 45: ...le on the Quatech web site all numbers in hex PCI Vendor ID 0x135C Quatech Inc PCI Device ID 0x01B0 DSCLP 200 300 0x01C0 SSCLP 200 300 PCI Class Code Base class 0x07 Simple communications controller Subclass 0x02 Multiport serial controller Interface 0x00 IRQ sourced by INTA Base address 0 0x80 bytes I O Reserved region Base address 1 0x10 bytes I O Serial ports Port 1 at offset 0x00 Port 2 at off...

Page 46: ...rs using adapter cable SSCLP one female D 9 connector Transceivers MAX 3076E or compatible Differential output 2V min with 50 ohm load RS 422 1 5V min with 27 ohm load RS 485 Output rise fall time 3ns min 40ns max 15ns typ Differential input threshold 0 2V min 0 2V max Input resistance 12k ohm min 15k ohm typ Input current 1 0mA max Power requirements 5 volts approx 320 mA Temperature operating 0 ...

Page 47: ...ifferent IRQ for the DSCLP 200 300 An address conflict is unlikely because most PCI based computers will assign I O addresses in such a way that they cannot conflict with ISA bus devices 3 The DSCLP 200 300 may be defective Contact technical support for instructions Cannot communicate with other equipment 1 Are the cable connections correct Are the cables securely attached 2 Is the software config...

Page 48: ...DSCLP SSCLP 200 300 User s Manual Revision 1 23 November 2006 P N 940 0182 123 i DSCLP SSCLP 200 300 User s Manual ...

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