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Quatech DS-1000, Owner'S Manual

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    I I I F .   L I N E   S T A T U S   R E G I S T E R

        +------+
    D7  | FFRX |----- Error in FIFO RCVR (FIFO only)
        +------+
    D6  | TEMT |----- Transmitter empty
        +------+
    D5  | THRE |----- Transmitter holding register empty
        +------+
    D4  |  BI  |----- Break interrupt
        +------+
    D3  |  FE  |----- Framing error
        +------+
    D2  |  PE  |----- Parity error
        +------+
    D1  |  OE  |----- Overrun error
        +------+
    D0  |  DR  |----- Data ready
        +------+

     Figure 12.  Line status register bit definitions.

FFRX - FIFO Receiver Error:

Always logic 0 in character mode.

FIFO mode:

I n d i c a t e s   o n e   o r   m o r e   p a r i t y   e r r o r s ,   f r a m i n g   e r r o r s ,
o r   b r e a k   i n d i c a t i o n s   i n   t h e   r e c e i v e r   F I F O .     F F R X   i s
reset by reading the line status register.

TEMT - Transmitter Empty:

I n d i c a t e s   t h e   t r a n s m i t t e r   h o l d i n g   r e g i s t e r   ( o r   F I F O )
a n d   t h e   t r a n s m i t t e r   s h i f t   r e g i s t e r   a r e   e m p t y   a n d   a r e
ready to receive new data.  TEMT is reset by writing a
character to the transmitter holding register.

THRE - Transmitter Holding Register Empty:

I n d i c a t e s   t h e   t r a n s m i t t e r   h o l d i n g   r e g i s t e r   ( o r   F I F O )
is empty and it is ready to accept new data.  THRE is
r e s e t   b y   w r i t i n g   d a t a   t o   t h e   t r a n s m i t t e r   h o l d i n g
register (or FIFO).

                             iv

Summary of Contents for DS-1000

Page 1: ...ation operation or general misuse voids all warranty rights Although every attempt has been made to guarantee the accuracy of this manual Qua Tech Inc assumes no liability for damages resulting from errors in this document Qua Tech Inc reserves the right to edit or append to this document at any time without notice Please complete the following information and retain for your records Have this inf...

Page 2: ...l not occur in a particular installation If this equipment does cause interference to radio or television reception which can be determined by turning the equipment o f f a n d o n t h e u s e r i s e n c o u r a g e d t o t r y t o c o r r e c t t h e interference by one or more of the following measures Reorient the receiving antenna Relocate the computer with respect to the receiver Move the co...

Page 3: ...ISTER 4 B INTERRUPT IDENTIFICATION REGISTER 5 C FIFO CONTROL REGISTER 7 D LINE CONTROL REGISTER 8 E MODEM CONTROL REGISTER 10 F LINE STATUS REGISTER 11 G MODEM STATUS REGISTER 13 H SCRATCHPAD REGISTER 14 IV FIFO INTERRUPT MODE OPERATION 14 V DIVISOR LATCH VALUES 14 VI ADDRESSING 15 VII INTERRUPTS 15 VIII PROGRAMMABLE OPTION SELECT 15 IX OUTPUT CONFIGURATIONS 18 X INSTALLATION 22 XI SPECIFICATIONS ...

Page 4: ...Parity options 8 Figure 10 Word length and stop bit options 9 Figure 11 MODEM control register 10 Figure 12 Line status register 11 Figure 13 MODEM status register 13 Figure 14 Divisor latch options 14 Figure 15 POS implementation 16 Figure 16 Base address locations 17 Figure 17 Interrupt request levels 17 Figure 18 Typical RS 232 C communications link 18 Figure 19 RS 232 C connectors 19 Figure 20...

Page 5: ...ional FIFO mode that reduces CPU overhead at higher data rates The DS 1000 address and interrupt selections are selected through the Programmable Option Select POS using the IBM installation utilities In addition jumpers are provided on t h e D S 1 0 0 0 t o c o n f i g u r e t h e a d a p t e r a s D a t a T e r m i n a l E q u i p m e n t D T E o r D a t a C o m m u n i c a t i o n s E q u i p m...

Page 6: ...iv ...

Page 7: ... stop bits Automatic addition and removal of start stop and parity bits Independent and prioritized transmit receive and status interrupts Transmitter clock output to drive receiver logic T h e f o l l o w i n g p a g e s p r o v i d e a b r i e f s u m m a r y o f t h e i n t e r n a l r e g i s t e r s a v a i l a b l e w i t h i n t h e 1 6 5 5 0 A C E T h e registers are addressed as shown in ...

Page 8: ...e s i n t e r r u p t o n c l e a r t o send data set ready ring indicator and data carrier detect ELSI Receiver Line Status Interrupt W h e n s e t l o g i c 1 e n a b l e s i n t e r r u p t o n o v e r r u n parity and framing errors and break indication ETBEI Transmitter Holding Register Empty Interrupt When set logic 1 enables interrupt on transmitter register empty ERBFI Received Data Availa...

Page 9: ...nable When logic 1 indicates FIFO mode enabled IIDx Interrupt Identification Indicates highest priority interrupt pending if any See IP and Figure 5 NOTE IID2 is always a logic 0 in character mode IP Interrupt Pending When logic 0 indicates that an interrupt is pending a n d t h e c o n t e n t s o f t h e i n t e r r u p t i d e n t i f i c a t i o n r e g i s t e r m a y b e u s e d t o d e t e ...

Page 10: ...cates the receiver FIFO trigger level has been reached The interrupt is reset when the FIFO drops below the the trigger level Character Timeout FIFO mode only Indicates no characters have been removed from or input to the receiver FIFO for the last four character times and there is at least one character in the FIFO during this time The interrupt is cleared by reading the receiver FIFO Transmitter...

Page 11: ...ange from mode 0 to mode 1 DMA mode not supported on DS 1000 XRST Transmit FIFO Reset When set logic 1 all bytes in the transmitter FIFO a r e c l e a r e d a n d t h e c o u n t e r i s r e s e t T h e s h i f t register is not cleared XRST is self clearing RRST Receive FIFO Reset When set logic 1 all bytes in the receiver FIFO are cleared and the counter is reset The shift register is not cleare...

Page 12: ... e r t r a n s m i t t i n g h o l d i n g register and interrupt enable register BKCN Break Control When set logic 1 the serial output SOUT is forced to the spacing state logic 0 STKP Stick Parity F o r c e s p a r i t y t o l o g i c 1 o r l o g i c 0 i f p a r i t y i s enabled See EPS PEN and Figure 9 EPS Even Parity Select Selects even or odd parity if parity is enabled See STKP PEN and Figur...

Page 13: ...and Figure 10 WLSx Word Length Select Determines the number of bits per transmitted word See STB and Figure 10 STB WLS1 WLS0 Word length Stop bits 0 0 0 5 bits 1 0 0 1 6 bits 1 0 1 0 7 bits 1 0 1 1 8 bits 1 1 0 0 5 bits 1 1 0 1 6 bits 2 1 1 0 7 bits 2 1 1 1 8 bits 2 Figure 10 Word length and stop bit selections iv ...

Page 14: ... r a n s m i t t e r a n d r e c e i v e r i n t e r r u p t s s t i l l o p e r a t e n o r m a l l y M O D E M c o n t r o l i n t e r r u p t s a r e a v a i l a b l e b u t a r e n o w controlled through the MODEM control register B i t s O U T 2 O U T 1 R T S a n d D T R p e r f o r m i d e n t i c a l f u n c t i o n s o n t h e i r r e s p e c t i v e outputs When these bits are set logic 1...

Page 15: ...ors framing errors or break indications in the receiver FIFO FFRX is reset by reading the line status register TEMT Transmitter Empty Indicates the transmitter holding register or FIFO and the transmitter shift register are empty and are ready to receive new data TEMT is reset by writing a character to the transmitter holding register THRE Transmitter Holding Register Empty Indicates the transmitt...

Page 16: ... r s a r e d i s a b l e d u n t i l S I N g o e s t o t h e m a r k state logic 1 and a valid start bit is received FE Framing Error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit was a 0 bit spacing level PE Parity Error Indicates that the received data does not have the correct parity OE Overrun Error Indicates the receive buffer was ...

Page 17: ... Clear To Send Complement of the CTS input pin 36 B i t s D D C D T E R I D D S R a n d D C T S a r e t h e sources of MODEM status interrupts These b i t s a r e r e s e t w h e n t h e M O D E M s t a t u s register is read DDCD Delta Data Carrier Detect Indicates the Data Carrier Detect input pin 38 has changed state TERI Trailing Edge Ring Indicator I n d i c a t e s t h e R i n g I n d i c a ...

Page 18: ...ata available indicator is set and cleared along with the receive data interrupt above 3 The data ready indicator is set as soon as a character is transferred into the receiver FIFO and is cleared when the FIFO is empty V DIVISOR LATCH VALUES Desired Divisor Error Between Desired Baud Rate Latch Value and Actual Value 50 2304 75 1536 110 1047 0 026 150 768 300 384 600 192 1200 96 1800 64 2000 58 0...

Page 19: ...nterrupt identification register should be used to test for the source of the interrupt CAUTION T o m a i n t a i n c o m p a t i b i l i t y w i t h e a r l i e r p e r s o n a l computer systems the user defined output OUT 2 is used as an external interrupt enable and must be set active for interrupts to be acknowledged OUT 2 is accessed through the 16550 s MODEM control register VIII PROGRAMMAB...

Page 20: ... a D3 ADS12 Address select D2 ADS11 D1 ADS10 D0 CEN Card enable D7 CHEN2 Channel enable D6 INS21 Interrupt select D5 INS20 D4 ADS23 b D3 ADS22 Address select D2 ADS21 D1 ADS20 D0 0 Reserved Figure 15 DS 1000 POS implementation a POS location 102H b POS location 103H iv ...

Page 21: ...ial 4 0 1 0 0 4220H Serial 5 0 1 0 1 4228H Serial 6 0 1 1 0 5220H Serial 7 0 1 1 1 5228H Serial 8 1 0 0 0 83F8H 1 0 0 1 82F8H 1 0 1 0 B220H 1 0 1 1 B228H 1 1 0 0 C220H 1 1 0 1 C228H 1 1 1 0 D220H 1 1 1 1 D228H Figure 16 Available base addresses INSx1 INSx0 IRQ 0 0 3 0 1 4 1 0 7 1 1 9 Figure 17 Available interrupt levels iv ...

Page 22: ... n E q u i p m e n t D C E t o implement an RS 232 C communication link Data terminal equipment and data communication equipment have complementary pinouts to allow terminals and MODEMs to be connected directly using a one to one cable as shown in figure 21 a In many applications DCEs are unnecessary because of the short distances involved In these cases a custom cable called a null MODEM or MODEM...

Page 23: ...escription D 9 D 25 D 9 D 25 Data Carrier Detect DCD 1 8 1 8 Receive Data RxD 2 3 3 2 Transmit Data TxD 3 2 2 3 Data Terminal Ready DTR 4 20 6 6 Signal Ground 5 7 5 7 Data Set Ready DSR 6 6 4 20 Request To Send RTS 7 4 8 5 Clear To Send CTS 8 5 7 4 Ring Indicator RI 9 22 9 22 Figure 20 Connector definitions for RS 232 C iv ...

Page 24: ...o o DCD 8 22 RI o o RI 22 7 GND o o GND 7 a Typical DTE to DCE cable DTE DTE Device Device 3 RxD o o RxD 3 2 TxD o o TxD 2 4 RTS o o RTS 4 5 CTS o o CTS 5 20 DTR o o DTR 20 6 DSR o o DSR 6 8 DCD o o DCD 8 22 RI o o RI 22 7 GND o o GND 7 b Typical DTE to DTE null MODEM cable Figure 21 Cabling requirements for RS 232 devices iv ...

Page 25: ...D RTS o o P1 4 RTS o o P1 4 P1 8 o o CTS P1 8 o o CTS DTR o o P1 7 DTR o o P1 7 P1 6 o o DSR P1 6 o o DSR 6 12 6 12 b Jumper connections c Jumper connections for DTE configuration for DCE configuration Figure 22 DS 1000 output configuration jumpers Shown are jumpers for port 1 NOTE Connections are referenced by port and pin number e g P1 3 _ port 1 pin 3 P1 6 _ port 1 pin 6 iv ...

Page 26: ...ide 4 Replace system cover 5 Turn unit on and insert copy of reference diskette into drive A 6 Respond N to automatic configuration 7 Select Copy an option diskette and follow copying instructions 8 Select Set configuration 9 Select Change configuration or Run automatic configuration and follow installation instructions After the initial installation the reference diskette will contain the configu...

Page 27: ...nal 2 D 25 connectors male available using adapter cables provided Transmit drivers MC1488 or compatible Receive buffers MC1489 or compatible I O Address range See Figure 16 Interrupt levels IRQ 3 4 7 9 Power requirements I T I MS Supply 500mA 575mA 5 Volts 38mA 46mA 12 Volts 36mA 43mA 12 Volts I T Typical adapter current I MS Maximum statistical adapter current iv ...

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