I I I D . L I N E C O N T R O L R E G I S T E R
+------+
D7 | DLAB |----- Divisor latch access bit
+------+
D6 | BKCN |----- Break control
+------+
D5 | STKP |----- Stick parity
+------+
D4 | EPS |----- Even parity select
+------+
D3 | PEN |----- Parity enable
+------+
D2 | STB |----- Number of stop bits
+------+
D1 | WLS1 |--+
+------+ +-- Word length select
D0 | WLS0 |--+
+------+
Figure 8. Line Control Register bit definitions.
DLAB - Divisor Latch Access Bit:
D L A B m u s t b e s e t t o l o g i c 1 t o a c c e s s t h e b a u d r a t e
d i v i s o r l a t c h e s . D L A B m u s t b e s e t t o l o g i c 0 t o
a c c e s s t h e r e c e i v e r b u f f e r , t r a n s m i t t i n g h o l d i n g
register and interrupt enable register.
BKCN - Break Control:
When set (logic 1), the serial output (SOUT) is forced
to the spacing state (logic 0).
STKP - Stick Parity:
F o r c e s p a r i t y t o l o g i c 1 o r l o g i c 0 i f p a r i t y i s
enabled. See EPS, PEN, and Figure 9.
EPS - Even Parity Select:
S e l e c t s e v e n o r o d d p a r i t y i f p a r i t y i s e n a b l e d . S e e
STKP, PEN, and Figure 9.
PEN - Parity Enable:
E n a b l e s p a r i t y o n t r a n s m i s s i o n a n d v e r i f i c a t i o n o n
reception. See EPS, STPK, and Figure 9.
+--------------+---------+
| STKP EPS PEN | Parity |
+--------------+---------+
| x x 0 | None |
| 0 0 1 | Odd |
| 0 1 1 | Even |
| 1 0 1 | Logic 1 |
| 1 1 1 | Logic 0 |
+--------------+---------+
Figure 9. 16550 parity selections.
iv
Summary of Contents for DS-1000
Page 6: ...iv ...
