Manual for Advance 10T
Advanced Chipset Features Setup
Figure-5 Advanced Chipset Features Setup Menu
The following indicates the options for each item and describes their meaning.
Item
Option
Description
#"
Bank 0/1, 2/3, 4/5
Normal
These items are of selected DRAM read/
DRAM Timing
Medium
write timing. According to the different DRAM
Fast
to chose proper option for improve system
Turbo
performance.
SDRAM 8/10ns
#"
SDRAM Cycle
2/3
Define the CLT timing parameter of SDRAM.
Length
Latency Time = 2 clocks.
Latency Time = 3 clocks.
#"
DRAM Clock
Host Clk
DRAM frequency same as CPU FSB.
Hclk-33M
DRAM frequency is slower than CPU FSB by 33MHz.
#"
Memory Hole
15M-16M
Memory Hole at 15-16M is reserved for expanded
ISA card.
Disabled
Do not set this memory hole.
#"
P2C/C2P
Enabled
Enabled P2C/C2P concurrency.
Concurrency
Disabled
Disable P2C/C2P concurrency.
#"
System BIOS
Enabled
Beside conventioal memory, system BIOS area is
Cacheable
also cacheable.
Disabled
System BIOS area is not cacheable.
Award BIOS Description
