PCI 9656RDK- LITE Hardware Reference Manual v1.4
© 2006 PLX Technology, Inc. All rights reserved.
7
2.5 Synchronous Burst SRAM
A 100-pin, 7.5ns, 32K x 32 Micron Synchronous
Burst SRAM (U14) is used for Processor/Local
Bus data storage on the RDK. During Direct
Slave memory burst cycles, the SRAM performs
continuous back-to-back single read cycles or
single write cycles. The Xilinx CPLD SRAM
controller (U13) does all of the timing conversion
and generates the lower 8 address bits to the
SBSRAM. The SBSRAM takes 7 upper address
lines (LA16-LA10) directly from the PCI 9656
and 8 lower address lines (MA[9:2]) from the
SRAM controller. The data lines of the SRAM
are directly connected to the PCI 9656 local data
bus (LD31-LD0).
2.6 Xilinx
CPLD
A 5ns Xilinx XC9572XL-5TQ100C CPLD (U13)
is used as the SRAM controller, external
Processor/Local Bus arbiter, and chip select
generator.
The SRAM controller in the CPLD generates the
lower 8-bit memory address (MA[9:2]), SRAM
chip select (SRAMCS#), SRAM output enable
(SRAMOE#), and SRAM byte write enables
(SRAM_BW_[3:0]) to the SRAM. It latches the
starting address signals (LA[9:2] for C mode and
LAD[9:2] for J mode), and uses its built-in
internal address counter to advance the
addresses to the SRAM. The SRAM controller
also generates the active low ready signal
(READY#) to terminate normal PCI 9656
memory cycles and also generates the active
low (BTERM#) input to the PCI 9656 to break
the continuous burst memory cycle when its
internal address counter reaches the final count
(FFh).
The external Processor/Local Bus arbiter in the
CPLD accepts the Processor/Local Bus request
signals (LBR [1:0]) from Processor/Local Bus
masters, if there are any, and the bus request
from the PCI 9656 (LHOLD). It generates bus
grant signals LBG [1:0] to the Processor/Local
Bus masters and LHOLDA to the PCI 9656.
The chip select generator in the CPLD
generates the SRAM chip select (SRAMCS#)
and four additional active low chip selects for the
Processor/Local Bus devices. The chip select
signals are partially decoded from the upper four
address lines (LA31-LA28) on the
Processor/Local Bus. They can be re-
programmed by altering the CPLD Verilog code.
2.7 Test
Headers
The RDK board has six (6) 0.1”, 2x10 logic
analyzer headers (LAH1-LAH6) that follow the
HP format and can be used for probing or
prototype area extension. All PCI 9656
Processor/Local Bus signals, configuration and
status signals are well arranged within these
headers. Headers LAH1 and LAH2 contain
Processor/Local Bus address signals. Headers
LAH3 and LAH4 contain Processor/Local Bus
data signals. Headers LAH5 and LAH6 contain
Processor/Local Bus control and status signals.
These headers do not provide any power
source. Schematic page 6 provides the
connector signal details.
2.8 PLX Option Module Connector
The PLX Option Module Connector (J3)
assumes that the Processor/Local Bus is
configured for 32-bit multiplexed address/data
bus (J mode) operation. (See Section 2.12 for
details on re-configuring the RDK hardware for J
Mode operation.) It can be used for expansion
and prototyping. Both/either a master and/or a
slave device may be connected to this
connector, which resides at Processor/Local Bus
address range 1000 0000 – 1FFF_FFFFh. The
external arbiter in the CPLD uses CS0# to select
the POM module. Schematic page 5 provides
the connector signal details.
2.9 Hardware
Modules
2.9.1 RS-232
Interface
The RS-232 interface circuit combines a DB9
male connector (J2) with a Maxim RS-232
transceiver (U12). The transceiver chip can be
hardware configured or software programmed
as Data Terminal Equipment (DTE) or Data
Circuit Equipment (DCE). See Table 2-4 for
details.
Table 2-4. RS-232 Transceiver
Configuration
R44 (not installed)
DTE
mode
(default)
R45 (installed)
R44 (installed)
DCE
mode
R45 (not installed)
