PCI 9054RDK-LITE Hardware Reference Manual v1.3
© 2006 PLX Technology, Inc. All rights reserved.
5
3.1 Hardware
Memory
Map
The PCI 9054RDK-LITE board Processor/Local Bus memory map is shown in Table 3-1.
Table 3-1. PCI 9054RDK-LITE Memory Map
Address Range
Device
Chip Select
Comments
FFFF FFFF
8000 0000
Unused _ Available
7FFF FFFF
7000 0000
Unused
CS3#
Available &
Re-programmable
6FFF FFFF
6000 0000
Unused CS2# Available
&
Re-programmable
5FFF FFFF
5000 0000
Unused CS1# Available
&
Re-programmable
4FFF FFFF
4000 0000
J mode POM connector
CS0#
32-bit, multiplexed
address/data bus
3FFF FFFF
2002 0000
Unused _
_
2001 FFFF
2000 0000
Synchronous SRAM
32K x 32
SRAMCS#
8, 16, 32-bit access
1FFF FFFF
0000 0000
Unused _ Available
3.2 PCI
9054
The PCI 9054 PCI I/O Accelerator is the most
advanced general-purpose 32-bit, 33 MHz PCI
bus master device available in the market today.
It offers a robust PCI Specification v2.2
implementation enabling burst transfers up to
132 MB per second. The PCI 9054 incorporates
the industry-leading PLX data transfer engine,
including two intelligent DMA channels,
programmable Direct Slave and Direct Master
data transfer modes, and PCI messaging
functions.
Two DMA Channels
•
Two independent channels provide flexible
prioritization scheme
•
Direct hardware control of DMA including
Demand, Block, and Scatter/Gather modes
•
Programmable burst length, including
unlimited burst
•
Shuttle Mode automatic invalidation of used
DMA descriptors
•
Unaligned
transfer
support
•
Hardware End of Transfer (EOT) support
•
Support for PCI bus mastering from local
slave-only devices
•
Scatter-Gather list management
Summary of Contents for PCI 9054RDK-LITE
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