Building a Simple Voltage Source Inverter
limited amount of time to execute the required model calculations on the CPU prior to the start of the
next model time step.
Your Task:
1
Replace the half bridge power modules in Fig. 1 with discrete IGBT with Diode components that
you can find in the Elec Power Semiconductors section of the PLECS library. Use a Digital
In block from the PLECS RT Box library and connect it to the switch gate signals as shown in the
figure. Keep the rest of the model the same as in Fig. 1.
2
Deploy the model on the RT Box with the same discretization step size of
5e
−
6
seconds as before.
?
Connect to the External Mode and check the simulation Scopes. What do you see? Do the
current measurements show any unexpected characteristics?
A
The “PWM” Scope should show six PWM signals which are either zero or one. The “Cur-
rent” Scope will show a balanced three-phase sinusoidal inductor current. However, you
will also notice a periodic oscillation on the peak current magnitude and additional har-
monic distortion compared to the results from the previous exercise. This is a consequence
of the limited PWM resolution.
3
Disconnect from the External Mode and change the discretization step size to
2e
−
6
seconds. Build
the model and deploy it to the RT Box. Connect to the External Mode and check the simulation
Scopes.
?
Do the real-time simulation results seem reasonable?
A
Decreasing the discretization time step from
5e
−
6
seconds to
2e
−
6
seconds helps to improve
the PWM resolution. There is a corresponding reduction in the distortion and non-ideal
characteristics of the current waveform under these operating conditions.
?
What is the execution time of the model and processor loading? These performance metrics
can be accessed from the RT Box Web Interface. Can the model complexity be increased?
A
The processor loading will be near
100 %
with an execution time of
2
.
0
µ
s
. The model com-
plexity cannot be further increased.
4
Disconnect from the External Mode. Add the Sine Wave Generator to the parameter inlining ex-
ceptions list. Once again, build the model and deploy it to the RT Box maintaining a discretization
step size of
2e
−
6
second.
After deploying the model and connecting via the External Mode, change the Sine Wave amplitude
from
1
.
0
to
0
.
2
.
?
Do the real-time simulation results seem reasonable? Why is the simulation sensitive to
these conditions? With a
2e
−
6
seconds discretization step size and a 10 kHz PWM signal,
is there a limit to the total number of achievable switch duty cycles with a conventional
switch model?
3