XW-HTD640
14
1
2
4
1
2
3
4
C
D
F
A
B
E
3. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM
3.1 BLOCK DIAGRAM
A
TX ASSY
J
TX MODULE
K
RX MODULE
D
OP ASSY
TRANSMITTER SECTION
Ch. select
1
3
8
CN8201
(12P)
H2
(12P)
Ch.1
U1
FS2105TX
Freesystems
Tx Chip
JA8202
L
R
WIRERESS
INPUT
DC IN
JA8001
ANT1
V+12
V+9RF
+9V
+9V
VA+9
IC8001
BA09FP
9V REG.
3
U7
EEPROM for FS
U9
AK5380VT
A/D Converter
U23
AWD601TX
RF Tx Module
11
9
10
IC8501
BU4052BCF
Ch Select SW.
3
2
R
D5V
U21
AIC1734-50CXA
REG.
3
2
A5V
U6
NCP1117ST50T3
5V REG.
3
2
D3V3
U22
AIC1734-33CXA
3.3V REG.
VD+9
A5V
2
3
D5V
U17
NCP1117ST50T3
5V REG.
D3V3
2
3
A3V3
U19
AIC1734-33CXA
3.3V REG.
D5V
2
3
R
U12
AIC1734-50CXA
5V REG.
SURROUND
STEREO
6
2
3
4
11
12
8
6
2
2
3
4
11
12
Q8506
Q8501
Ch.2
15
Q8502
Ch.3
14
Q8503
Ch.4
12
Q8504
Q8505
LED 2
LED 1
CHSEL
H3
(12P)
CN3701
(12P)
CN3051
(13P)
CN3504
(13P)
8
12
11
V+9
LVIN
RVIN
LVOUT
RVOUT
VA+9
VREF
V+9
LOUT
ROUT
6
5
1
2
7
7
9
8
1
6
7
5
8
1
6
LIN
AINL
SDTO
SDTO
RFOUT
CHANNEL1
CHANNEL2
CHANNEL3
H10
52806-0910
EEPROM Prog.
Interface
U11
EEPROM for FS
VCXO1-VCXO8
H6
52807-0910MOLEX
EEPROM Prog.
Interface
CLKIN
CLKOUT
1
9
13
U3
AIC1680
System
Power On Reset
1
58
31 33 34 35
CHANNELBIT1
PLD02
RESET
64
11
CHANNELBIT2
PLD01
CHANNELSEL
12
CHNNELSEL
8
AINR
12
RFINANT
RFANT1
DATA
1
CHAN2
8
CHAN1
9
CHAN3
7
RIN
V+9RF
V+9RF
X1
24.576MHz
3
5
RESETIN
DATA
1
7
5
3
VOUTL
X2
12.288MHz
+9V
V+9RF
VREF
VA+9
VREF
VA+9
+9V
Mode
ANT2
ANT3
SDTI
VCLKIN
58
17
14
U18
NC7SPU04
P5X
VCXO
U28
PCM1742KE
D/A Converter
U24
NJM4558
DAC Filter
7
54
2
4
6
2
7
VOUTR
8
Y0
X0
Y1
X1
Y (Rch)
X (Lch)
IC3001
BU4052BCF
Selecter
1
12
5 14
13
9
3
7
1
3
5
IC3301
NJM4558MD
IC3051
NJM4558MD
VR3051
VOL
3
1
4
4
13
13
5
7
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