XV-DV830
130
1
2
4
1
2
4
C
D
F
A
B
E
Symbol
Pin
Type
[1]
Description
H_A[1]
1
IN
address bus
H_DQ[15]
2
I/O10
data bus
H_DQ[14]
3
I/O10
data bus
GND_IO1
4
GND_IO
GND I/O pads
H_DQ[13]
5
I/O10
data bus
H_DQ[12]
6
I/O10
data bus
H_DQ[11]
7
I/O10
data bus
H_DQ[10]
8
I/O10
data bus
H_DQ[9]
9
I/O10
data bus
VCC_IO1
10
VCC_IO
V
CC
I/O pads
H_DQ[8]
11
I/O10
data bus
H_DQ[7]
12
I/O10
data bus
H_DQ[6]
13
I/O10
data bus
H_DQ[5]
14
I/O10
data bus
H_DQ[4]
15
I/O10
data bus
H_DQ[3]
16
I/O10
data bus
GND_IO2
17
GND_IO
GND I/O pads
H_procclock
18
IN
host processor EMI interface clock
VCC_Core1
19
VCC_core
core supply voltage
GND_Core1
20
GND_core
core ground
sys_clk
21
IN
system clock
H_DQ[2]
22
I/O10
data bus
H_DQ[1]
23
I/O10
data bus
H_CSn
24
IN
host chip select; active LOW
H_DQ[0]
25
I/O10
data bus
H_RWn
26
IN
read = 1; write = 0
H_WAIT
27
O10
wait signal
H_IRQn
28
O10
interrupt request; active LOW
IN
DSD audio clock
IN
PCM data clock
IN
PCM word clock
VDDCO
V
DD
of ADC
VSSCO
V
SS
of AGC and ADC; connected to substrate
APIO
bias current input
APIO
AGC positive input signal; HF in
APIO
ADC decoupling
VCC_IO7
37
VCC_IO
V
CC
I/O pads
GND_IO7
38
GND_IO
GND I/O pads
PCM_CeLf_in
39
IN
PCM data center or LFE
¶
Pin Function
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8
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0
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3
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