VSX-AX5i-S
163
5
6
7
8
5
6
7
8
C
D
F
A
B
E
Pin Function
No.
Pin Name
I/O
Pin Function
Active
1
12VTRIGGER
O
"H" at ON
2
–
O
NC "L" fixed.
3
1394 RST
O
Reset for 1394
4
1394 CS
O
Standby for 1394 (Not used) "L" fixed.
5
1394 DO
O
DO for 1394
6
1394 DI
I
DI for 1394
7
1394 CK
O
CK for 1394
8
GND
−
Ground
9
CNVSS
−
5.1k
Ω
pulldown
10
–
O
L" fixed
11
–
O
L" fixed
12
XRESET
−
Reset
13
XOUT
−
Oscillator
14
GND
−
Ground
15
XIN
−
Oscillator
16
5V
−
5V power supply
17
NMI
I
Cannot use it as usual input port (100k
Ω
pullup)
18
WAKEUP
I
Wakeup
H
19
1394 INT
I
INT for 1394
20
1W WUP
I
Wakeup signal at standby (from the display microcomputer) (pulldown)
H
21
–
O
L" fixed
22
DISP EN
O
Communication enabling signal to the display microcomputer
H
23
OSD RST
O
OSD-IC reset signal L: reset, H: release reset
24
OSD CS
O
OSD-IC chip select signal
H
25
OSD CONT.
O
At data transfer to the OSD-IC: "H"
26
DISP RST
O
Display microcomputer reset signal L: reset, H: release reset (pulldown)
27
DISP RDY
I
Communication enabling signal from the display microcomputer
H
28
OSD/DISP CLK
O
Communication clock signal with the OSD-IC/display microcomputer
29
DISP DO
I
Communication data in signal with the display microcomputer (N ch open drain)
30
OSD/DISP DI
O
Communication data out signal with the OSD-IC/display microcomputer (N ch open drain: pullup)
31
232C RXD
O
For 232C rewriting (data output)
32
232C TXD
I
For 232C rewriting (data input)
33
CLK
O
Not used
34
232C CTS
O
For 232C rewriting (communication permission)
35
DSP DI
O
Communication data out signal with the DSP1 microcomputer
36
DSP DO
I
Communication data in signal with the DSP2 microcomputer
37
DSP CLK
O
Communication clock signal with the DSP microcomputer
38
DSP1 RST
O
DSP1 microcomputer reset signal L: reset, H: release reset
39
DSP2 RST
O
DSP2 microcomputer reset signal L: reset, H: release reset
40
DSP1 SS
O
Slave select signal to DSP1 microcomputer
L
41
DSP2 SS
O
Slave select signal to DSP2 microcomputer
L
42
DSP MODE1
O
Mode selection of DSP1 microcomputer (ROM/RAM) H: ROM mode, L: RAM (PPP) mode
H
43
DSP MODE2
O
Mode selection of DSP2 microcomputer (ROM/RAM) H: ROM mode, L: RAM (PPP) mode
H
44
DIR DI
O
Communication data out signal with the DIR
45
DIR DO
I
Communication data in signal with the DIR/DAC
46
DIR CS
O
Communication chip select signal with the DIR/DAC
47
DIR CK
O
Communication clock signal with the DIR/DAC
48
DIR ERR
I
Lock/Unlock signal
49
DIR RST
O
DIR reset signal
50
DECO MUTE
I
Boot success detecting port of 1st DSP
Summary of Contents for VSX-AX3-K
Page 7: ...VSX AX5i S 7 5 6 7 8 5 6 7 8 C D F A B E ...
Page 23: ...VSX AX5i S 23 5 6 7 8 5 6 7 8 C D F A B E 3 1 4 POWER AMP BLOCK DIAGRAM ...
Page 25: ...VSX AX5i S 25 5 6 7 8 5 6 7 8 C D F A B E ...
Page 31: ...VSX AX5i S 31 5 6 7 8 5 6 7 8 C D F A B E ...
Page 52: ...VSX AX5i S 52 1 2 3 4 1 2 3 4 C D F A B E 3 15 1394 ASSY 1 2 VSX AX5i S ONLY T 1 2 For Flash ...
