PRO-700HD
238
7
SAA4952WP (SUB VIDEO ASSY: IC4704)
MEMORY CONTROLLER
¶
Pin Assignment
¶
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ALE
WRD
P0
P1
P2
P3
P4
P5
P6
P7
STROBE
LLA
(12,13.5,16,18MHz)
TEST
SDP
SSC
VACQ
(50/60Hz)
LLDFL
(27,32,36MHz)
LLD
(32,36MHz)
DEFLECTION
TIMING
LOGIC
V
SS
1 to V
SS
4
V
DD
1 to V
DD
4
SRC
HRD
BLND
RE2
RE1
HVCD
WE2
VDFL
HDFL
HRDFL
RSTW1
WE1
CLV
HRA/BLNA
SWC05
SWC1
IE2
IE1
MICROCONTROLLER INTERFACE
SAA4952WP
IE
PROCESSING
+2
ACQUISITION
HORIZONTAL
TIMING
ACQUISITION
VERTICAL
TIMING
HWE1
VACQS
LOGIC
LOGIC
VWE1
DISPLAY
VERTICAL
TIMING
DISPLAY
HORIZONTAL
TIMING
VWE2
VRE1
VRE2
VD
HWE2
HRE
HD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SAA4952WP
IE1
WE1
STROBE
HRA/BLNA
LLA
IE2
CLV
WE2
HVCD
VACQ
HRDFL
VDFL
LLDFL
HDFL
P7
P6
P5
P4
SWC05
SDP
SRC
SWC1
HRD
V
DD1
V
SS4
V
SS2
V
DD3
LLD
RSTW1
SSC
TEST
RE1
RE2
BLND
ALE
WRD
P0
P1
P2
P3
V
SS1
V
DD2
V
DD4
V
SS3
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Name
HRD
VDD 1
SWC1
SRC
SDP
SWC05
IE1
WE1
STROBE
VCC 2
HRA/BLNA
VSS 1
LLA
IE2
WE2
CLV
HVCD
RE1
Function
Horizontal reference signal output (display PLL)
Supply voltage 1
Serial write clock output for memory 1
Serial read clock output
Select deflection processor input
Serial write clock output,SWC1 divided-by-2
Input enable signal output (memory 1)
Write enable signal output (memory 1)
Strobe signal input
Supply voltage 2
Horizontal reference signal output (acquisition part)/horizontal blanking signal input,reset for
horizontal acquisition counters(acquisition part)
Ground 1
Line- locked cloack signal input (acquisition part)
Input enable signal output (memory 2)
Write enable signal output (memory 2)
Horizontal signal output (acquisition part)
Horizontal,vertical or composite blanking signal output (display part)
Read enable signal output (memory 1)
¶
Pin Function
I/O
O
—
O
O
I
O
O
O
I
—
I/O
—
I
O
O
O
O
O
