PDP-507XD
127
5
6
7
8
5
6
7
8
C
D
F
A
B
E
SUS-B ADJUSTMENT
50X MAIN DRIVE Assy
SUS-D ADJUSTMENT
XSUS-U
from
DIGITAL Assy
IC1001_A2
Pin
3
Pin
2
Pin
5
Pin
4
Pin
8
Pin 2
IC1102
IC1205
IC1101
IC1104
X DK
Module
Q1102
TP1106
Photo
Coupler
1
Measure the SUS-U input delay time (
∆
Tsus-u).
from
DIGITAL Assy
XSUS-B
IC1001_A1
VR1001
Q1210
FET
Q1211
FET
Photo
Coupler
IC1204
Q1213
Q1209
TP1260
2
Adjust the SUS-B input delay time so that it becomes "
∆
Tsus-u +
α
±
5 nsec."
50Y MAIN DRIVE Assy
50Y MAIN DRIVE Assy
YSUS-U
from
DIGITAL Assy
IC2003_A4
Pin 2
IC2102
IC2209
IC2101
IC2107
Y DK
Module
Q2103
TP2105
Photo
Coupler
1
Measure the SUS-U input delay time (
∆
Tsus-u).
1
Measure the SUS-D pulse width (Tsus-D).
from
DIGITAL Assy
YSUS-B
IC2003_A4
VR2001
Q2210
FET
Q2216
FET
Photo
Coupler
IC2208
Q2221
Q2215
TP2276
2
Adjust the pulse width of the SUS-D input signal for
the DK module so that it becomes "Tsus-D
±
5 nsec."
2
Adjust the SUS-B input delay time so that it becomes "
∆
Tsus-u +
α
±
5 nsec."
from
DIGITAL Assy
YSUS-D
IC2002_A7
Q2106
VR2002
IC2104
IC2107
Y DK
Module
TP2107
Summary of Contents for PDP-507XA
Page 41: ...PDP 507XD 41 5 6 7 8 5 6 7 8 C D F A B E ...
Page 44: ...PDP 507XD 44 1 2 3 4 1 2 3 4 C D F A B E 4 2 OVERALL CONNECTION DIAGRAM 2 2 ...
Page 45: ...PDP 507XD 45 5 6 7 8 5 6 7 8 C D F A B E ...
Page 55: ...PDP 507XD 55 5 6 7 8 5 6 7 8 C D F A B E ...
Page 78: ...PDP 507XD 78 1 2 3 4 1 2 3 4 C D F A B E 500ns div 500ns div 200ns div ...
Page 191: ...PDP 507XD 191 5 6 7 8 5 6 7 8 C D F A B E Block Diagram R2S11002AFT MAIN ASSY IC4701 AV SW ...