Pioneer PDP 503CMX, Service Manual

Page: 157 / 167

PDP-503CMX
157
5 6 7 8
5 6
7
8
C
D
F
A
B
E
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
A/B MUX
RINA/YINA
GND
VCC
RINB/YINB
GINA/UINA
GINB/UINB
BINA/VINA
SYNC IN
DISABLE
GNDO
ROUT/YOUT
VCCO
GOUT/U OUT
BOUT/VOUT
BINB/VINB
Pin Assignment (Top view)
Block diagram
Pin Function
ML6426CS1 (RGB ASSY: IC4403)
LPF IC
RINA/YINA
2
RINB/YINB
BINA/VINA
8
BINB/VINB
9
A/B MUX
GINA/UINA
6
GIN/U INB
7
ROUT/YOUT
13
GOUT/U OUT
11
BOUT/VOUT
10
4th-ORDER
FILTER A
4th-ORDER
FILTER B
4th-ORDER
FILTER C
MUX
MUX
MUX
2
2
2
TRANSCONDUCTANCE
ERROR AMP
TRANSCONDUCTANCE
ERROR AMP
TRANSCONDUCTANCE
ERROR AMP
1
SYNCIN
16
GNDO
14
DISABLE
15
VCCO
12
VCC
4
GND
3
5
+
–
+
–
+
–
0.5V
0.5V
0.5V
PIN NAME FUNCTION
1 A/B MUX Logic input pin to select between
Bank <A> and Bank <B> video inputs.
This pin is internally pulled high.
2 R
IN
A/Y
IN
A Unfiltered analog R- or Y-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
3 GND Analog ground
4 V
CC
Analog 5V supply
5 R
IN
B/Y
IN
B Unfiltered analog R- or Y-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
6 G
IN
A/U
IN
A Unfiltered analog G- or U-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
7 G
IN
B/U
IN
B Unfiltered analog G- or U-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
PIN NAME FUNCTION
8 B
IN
A/V
IN
A Unfiltered analog B- or V-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
9 B
IN
B/V
IN
B Unfiltered analog B- or V-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
10 B
OUT
Analog B or V-channel output
11 G
OUT
Analog G or U-channel output
12 V
CCO
5V power supply for output buffers
13 R
OUT
Analog R or Y-channel output
14 GNDO Analog ground
15 DISABLE Disable/Enable pin. Turns the chip off
when logic high. Internally pulled low.
16 SYNC IN Input for an external H-sync logic
signal for filter channels. CMOS
level input. Active High.