FX-MG9107ZT/UC
94
1
2
4
1
2
3
4
C
D
F
A
B
E
-
Pin Functions(PE5455A)
Pin No.
Pin Name
I/O Format
Function and Operation
1
AVREF
A power supply Positive power supply(5V)
2
AVSS
A power supply GND
3
EMP
O
C
The evaluation terminal for shocking proofs
4
CLAMP
I
Clamp SW sense input
5
EVDD
E power supply Positive power supply
6
CAMVOL O
C
CAM motor driver output voltage change
g
g
7
E/LVOL1 O
C
ELV/LOAD motor driver output voltage change
g
g
8
IC/FLMD0
IC : VSS direct connection/FLMOD0 : Pull-down
9
VDD
Positive power supply(5V)
y(
)
10
REGC
Connected to the capacity stabilizing output of the regulator
y
g
g
11
VSS
GND
12
X1
I
Oscillator connection for mainclock
13
X2
Oscillator connection for mainclock
14
reset
I System reset input
15
XT1
I
Connected to the oscillator for subclock
16
XT2
Connected to the oscillator for subclock(Open)
17
PULLDOWN
Connected to EVDD or EVSS via the resistor
18
EMC
The evaluation terminal for shocking proofs
g
19
xint
I
C
CD LSI interruption signal input
g
20
NC
Connected to VSS via the resistor
21
brst
I
IIC-Bus reset input
22
BSI
I
IIC-Bus serial data input
23
BSO
O C
IIC-Bus serial data output
24
bsck
O
C
IIC-Bus clock output
25
FTXD
O C
For flash rewriting(transmitted signal)
g(
g
)
26
FRXD
I
For flash rewriting(received signal)
g(
g
)
27
BRXEN
I/O
/C
IIC-Bus reception enable input/output
28
BSRQ
I/O
/C
IIC-Bus request input/output
q
29
NC
Not
used
30
E/LVOL2
O C
ELV/LOAD motor driver output change
g
31
E/LREV
O C
ELV/LOAD motor control output(REV)
32
E/LFWD
O C
ELV/LOAD motor control output(FWD)
(
)
33
EVSS
E power supply GND
y
34
EVDD
E power supply Positive power supply
y
y
35-37 RAM0-2
O
C
RAM level output
38
SPDFG
I
SPDL FG pulse input
39-42 NC
Not
used
43
INISW
I
Disc sense input for initialization
44
svcont
O
C
Standard voltage change output
g
g
45
epcs
I
BBOX sense input
46
NC
Not
used
O C
Servo driver power supply control output
y
C
CD LSI reset control output
O C
VD power supply control output
y
ROMDATA I/O
/C
E2PROM data input/output
O C
E2PROM chip selection output
O C
E2PROM clock output
C
Emphasis information output
DSPMUTE O C
DOUT mute output
O C
CD mute control output
It is EJECT at the time of L detection during 1 second
g
LOADSWL I
Load operation sense input
LOADSWR I
Load operation sense input
59
xcs
O
C
CD LSI chip selection output
60
ROM1K
I
EEPROM 2k/1k change input
g
61
xwait
I
CD LSI write control signal output
g
62
CLKOUT
O C
Internal system clock output(Open)
y
(
)
63
LOCK
I
Spindle lock input
64
NC
Not
used
65
xwrite
O
CD LSI write control signal output
g
www. xiaoyu163. com
QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
