35
DV-505, DVL-909, DV-S9
PD3381A (DVDM ASSY : IC601)
• System Control CPU
•
Block Diagram
79
RES
78
67
WDTOVF
82
MD2
81
MD1
80
MD0
76
NMI
77
15
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vpp
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
43
70
75
83
84
99
3
12
22
31
40
52
61
72
96
106
86
AVref
85
AVcc
91
AVss
71
CK
73
EXTAL
74
XTAL
PA13/IRQ1/DREQ0/TCLKB
66
PA12/IRQ0/DACK0/TCLKA
65
PA11/DPH/TIOCB1
64
PA10/DPL/TIOCA1
63
PA9/AH/IRQOUT/ADTRG
62
PA8/BREQ
60
PA7/BACK
59
PA6/RD
58
PA5/WRH(LBS)
57
PA4/WRL(WR)
56
PA3/CS7/WAIT
55
PA2/CS6/TIOCB0
54
PA1/CS5/RA5/RAS
53
PA0/CS4/TIOCA0
51
CS3/CASL
50
CS2
49
CS1/CASH
48
CS0
47
A21
46
A20
45
A19
44
A18
42
A17
41
39
A16
68
PA14/IRQ2/DACK1
69
PA15/IRQ3/DREQ1
A15
38
A14
37
A13
36
A12
35
A11
34
A10
33
A9
32
A8
30
A7
29
A6
28
A5
27
A4
26
A3
25
A2
24
A1
23
A0(HBS)
21
AD15
20
AD14
19
AD13
18
AD12
17
AD11
16
AD10
14
AD9
13
AD8
11
AD7
10
AD6
9
AD5
8
AD4
7
AD3
6
AD2
5
AD1
4
AD0
PB0/TP0/TIOCA2
PB1/TP1/TIOCB2
100
PB2/TP2/TIOCA3
101
PB3/TP3/TIOCB3
102
PB4/TP4/TIOCA4
103
PB5/TP5/TIOCB4
104
PB6/TP6/TOCXA4/TCLKC
105
PB7/TP7/TOCXB4/TCLKC
107
PB8/TP8/RxD0
108
PB9/TP9/TxD0
109
PB10/TP10/RxD1
110
PB11/TP11/TxD1
111
PB12/TP12/IREQ4/SCK0
112
PB13/TP13/IREQ5/SCK1
PB14/TP14/IREQ6
PB15/TP15/IRQ7
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
95
PC7/AN7
OSCILLATOR
94 93 92 90 89 88 87
2
1
98 97
PORT A
ADDRESS
PORT B
PORT C
WATCHDOG
TIMER
A/D
CONVERTER
PROGRAMABLE
TIMING
PATTERN
CONTROLLER
SERIAL
COMMUNICATION
INTERFACE
(
×
2CHANNEL)
16BIT
INTEGRATED
TIMER PULSE UNIT
BUS STATE
CONTROLLER
INTERRUPT
CONTROLLER
USER BREAK
CONTROLLER
CPU
DIRECT
MEMORY
ACCESS
CONTROLLER
64k PROM / MASK ROM
4kB RAM1
ADDRESS
DATA/ADDRESS
Periphery address bus(24 bit)
Periphery data bus(16 bit)
Internal address bus(24 bit)
Internal upper data(16 bit)
Internal lower data(16 bit)
Summary of Contents for DVL-K88
Page 33: ...DVL K88 33 ...
Page 84: ...84 DVL K88 8 PANEL FACILITIES AND SPECIFICATIONS FRONT PANEL ...
Page 85: ...85 DVL K88 DISPLAY WINDOW ...
Page 86: ...86 DVL K88 REMOTE CONTROL ...
