115
DV-AX10
.
o
N
e
m
a
N
n
i
P
O
/
I
n
o
i
t
c
n
u
F
n
i
P
1
0
2
9
1
_
D
N
G
−
.
)
V
0
(
e
g
a
t
l
o
v
e
c
n
e
r
e
f
e
r
o
t
t
c
e
n
n
o
C
d
n
u
o
r
G
2
0
2
1
0
_
T
I
.
D
N
G
o
t
t
c
e
n
n
o
C
t
u
p
n
i
n
i
p
e
d
o
m
t
s
e
T
3
0
2
2
0
_
T
4
0
2
K
C
O
L
G
S
O
"
H
"
:
k
c
o
l
t
a
t
u
p
t
u
o
l
a
n
g
i
s
k
c
o
l
G
S
S
5
0
2
N
R
S
I
t
u
p
n
i
t
t
i
m
h
c
S
t
e
s
e
r
:
L
t
u
p
n
i
t
e
s
e
r
m
e
t
s
y
S
6
0
2
K
L
C
S
I
t
u
p
n
i
t
t
i
m
h
c
S
.
e
g
d
e
g
n
i
s
i
r
t
a
A
T
A
D
S
n
i
d
a
e
L
e
c
a
f
r
e
t
n
i
l
a
i
r
e
s
U
P
M
f
o
t
u
p
n
i
k
c
o
l
C
7
0
2
A
T
A
D
S
I
t
u
p
n
i
t
t
i
m
h
c
S
e
c
a
f
r
e
t
n
i
l
a
i
r
e
s
U
P
M
f
o
t
u
p
n
i
a
t
a
D
8
0
2
B
S
C
I
t
u
p
n
i
t
t
i
m
h
c
S
t
c
e
l
e
s
:
L
e
c
a
f
r
e
t
n
i
l
a
i
r
e
s
U
P
M
r
o
f
t
u
p
n
i
t
c
e
l
e
s
p
i
h
C
CY2071ASL-371 (DVDM ASSY : IC965)
• PLL Clock Generator
•
Block Diagram
•
Pin Function
3
4
1
5
6
XTALIN
XTALOUT
CLKA
CLKB
CLKC
Reference
Oscillator
EPROM
Configurable
Multiplexer
and Divide
Logic
PLL
Block
8
OE/FS
No. Pin Name
Function
1
CLKA
Configurable clock output
2
GND
Ground
3
XTALIN
Reference crystal input or external
reference clock input
4
XTALOUT
Reference crystal feedback
5
CLKB
Configurable clock output
6
CLKC
Configurable clock output
7
VDD
Voltage supply
8
OE/FS
Output control pin, either output enable
or frequency select input. (Active-High,
internal pull-up resistor to VDD)
www. xiaoyu163. com
QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
