DJM-800
128
1
2
3
4
1
2
3
4
C
D
F
A
B
E
7.2 POWER ON SEQUENCE
Power ON Sequence
Power ON
Release the CPU reset
Interrupt mask
Mute ON
CPU initialization
RAM clear
Interrupt enable
TSTR timer interrupt set
Display a model name in FL
FPGA program load
(470ms)
Release the FPGA reset
DSP reset
Release the DSP reset
WAIT (10m sec)
Release the reset when pin 92
of IC1 is H.
Pin 3 of IC1 is H.
Data and clock outputs with pins
142 and 138 of IC1.
Control with pins 57 and 58.
Clear the FPGA program when
pin 24 of IC1 is H. Data and clock
outputs with pins 137 and 141.
Load is completed normally when
pin 71 of IC13 is H.
Release the reset when pin 27
of IC1 is H.
Wait for 30ms when pin 26 of IC1
is H, and wait for 60ms with L,
then reset it.
Release the reset when pin 26 of
IC1 is H. Also release the reset
the IC904, IC1501, IC918, IC409,
IC509, IC609, IC709, IC1307,
IC1308, IC1202, IC1203, IC1208,
IC1209, IC1214, IC1215, IC1217,
IC1218 and IC12 with this pin.
WAIT (10 msec)
Initial setting of the work
DIT initialization
Test mode ?
WAIT (500 msec)
Data and clock outputs with pins
142 and 138 of IC1.
Bootwait of DSP
DAC initialization
Data and clock outputs with pins
133 and 135 of IC1.
DIR initialization
WAIT (4000 msec)
4CH realtime initialization.
Data output with pins 10 and 13
of IC13, and clock output with
pins 11 and 14.
Waits for noise rejection
Mute OFF
Starts the LED display
Starts the key scan
Pin 3 of IC1 is L
Test mode processing
Main processing
MIDI CH setting
mode ?
No
No
Yes
MIDI CH setting mode
processing
Yes
Summary of Contents for DEJC-800RV
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