16
BDP-LX55
1
2
3
4
A
B
C
D
E
F
1
2
3
4
4.2 BLOCK DIAGRAM FOR POWER BLOCK
1
2
4
+5V
+12
VCC
U1
1. 1V
OPWRSB
U6
1. 5V
EN
U
3
3
.
3
V
EN
U16
U15
1V
8
1V
EN
1. 2V
G5725
U14
88
DE2750
FB12
1V_KYOTO_G2
L9
G5725
U42
Sii91
3
6
FB6
FB7
FB
3
2
FB
8
FB10
1V
8
_KYOTO_G2_DDR2
G9661
FB11
3
V
3
_KYOTO_G2
U7
MT
8
555
DCDC
Conv.
DCDC
Conv.
L1
L
3
AT1526
AT1529
DCDC
Conv.
L10
DCDC
Conv.
22
2.2
u
2.2
u
2.2
u
R101
0
AVDD12_MEMPLL
R41
3
R414
AVDD12_USB_1P_1
AVDD12_USB_2P_1A
R407
AVDD12_SATA1
R427
R42
8
AVDD12_COM
AVDD12_REC
R651
AVDD12_HDMI_RX
AVCC12
CVCC12
R25
A1. 2V
PLL BLOCK
0
U
8
H5TQ1G6
3
BFR
DDR
3
U9
H5TQ1G6
3
BFR
DDR
3
U10
H5TQ1G6
3
BFR
DDR
3
U11
H5TQ1G6
3
BFR
DDR
3
0
0
0
0
0
0
6
-24V
1
2
4
6
6
9
10
R109
R110
DDR_VREF
FB5
CAVCC
33
IOVCC
33
U4
3
PD7
8
F1164
FB24
3
.
3
VU
R
3
40
R
3
41
RESET
CIRCUIT
RESET
CIRCUIT
U2
G9091
FB
3
Y4
VCXO
3
.
3
V_STBY
FB4
U
3
1
TS5A
3
157
R52
R54
R57
AVDD
33
_VDAC_R
AVDD
33
_VDAC_X
AVDD
33
_VDAC_BG
R400
R402
R410
AVDD
33
_SATA
AVDD
33
_1P_1
AVDD
33
_2P_2
R429
R4
3
0
R4
3
1
AVDD
33
_COM
AVDD
33
_REC
AVDD
33
_LD
R660
AVDD
33
_HDMI_RX
FB1
8
3
.
3
V
FB**
1V
8
_FOR_Xt
a
l
U401
NAND Fl
a
sh
+12
-24V
XP1
CN50
3
MAIN BOARD ASSY
A
POWER BOARD ASSY
E