System
Memory
©
PHYTEC Meßtechnik GmbH 2009 L-719e_2
33
6
System Memory
In principle, two different memory models are available. The first
memory model is the one that is active after a reset. The run time
memory model, in contrast, is configured via software by the
application.
6.1
Memory Model following Reset
The internal Chip Select logic provided by the TC1796 controller is
used exclusively on the phyCORE-TC1796. Hence the memory model
as described in the TC1796 User's Manual is valid after reset.
6.2
Runtime Memory Model
The runtime memory model is configured via software using the
internal registers of the TC1796. There is a register set containing a
BUSCON, BUSAP and ADDSEL register for each of the controllers
Chip Select signals. The values in the Bus Configuration Registers
(EBU_BUSCON0-3 and EBU_BUSAP0-3) inform the processor of
how it should access the connected memory devices (wait states, bus
width, etc.). The Address Selection Registers (EBU_ADDSEL0-3)
define the address range in which the corresponding Chip Select
signal is active. The following list shows the settings for the Chip
Select signal assignment.
/CS0
on-board Flash memory or free
/CS1
on-board SRAM bank A or free
/CS2
on-board SRAM bank B or free
/CS3
on-board ethernet controller or free
/CSCOMB free