L-1017e.A3 i.MX 8M Plus BSP Manual
Accessing Peripherals
To find out which boards and modules are supported by the release of PHYTEC’s phyCORE-i.MX 8M Plus BSP
described herein, visit our web page
https://www.phytec.de/produkte/system-on-modules/phycore-imx-8m-plus/
and click the corresponding BSP release in the download section. Here you can find all hardware supported in the
columns "Hardware Article Number" and the correct machine name in the corresponding cell under "Machine
Name".
To achieve maximum software re-use, the
Linux
kernel offers a sophisticated infrastructure that layers software
components into board-specific parts. The BSP tries to modularize the kit features as much as possible. This means
that when a customized baseboard or even a customer-specific module is developed, most of the software support
can be re-used without error-prone copy-and-paste. The kernel code corresponding to the boards can be found in
device trees (DT) under
linux/arch/arm64/boot/dts/freescale/*.dts*
.
In fact, software re-use is one of the most important features of the
Linux
kernel, especially of the ARM
implementation which always has to fight with an insane number of possibilities of the System-on-Chip CPUs. The
whole board-specific hardware is described in DTs and is not part of the kernel image itself. The hardware
description is in its own separate binary, called the Device Tree Blob (DTB) (section
).
PHYTEC i.MX 8M Plus BSP Device Tree Concept
to get an understanding of our i.MX 8 BSP device
tree model.
The following sections provide an overview of the supported hardware components and their operating system
drivers on the i.MX 8 platform. Further changes can be ported upon customer request.
i.MX 8M Plus Pin Muxing
The
i.MX 8M Plus SoC
contains many peripheral interfaces. In order to reduce package size and lower overall system
cost while maintaining maximum functionality, many of the i.MX 8M Plus terminals can multiplex up to eight signal
functions. Although there are many combinations of pin multiplexing that are possible, only a certain number of
sets, called IO sets, are valid due to timing limitations. These valid IO sets were carefully chosen to provide many
possible application scenarios for the user.
NXP i.MX 8M Plus Reference Manual
for more information about the
specific pins and the muxing capabilities.
The IO set configuration, also called muxing, is done in the Device Tree. The driver
pinctrl-single
reads the DT's
node
fsl,pins,
and does the appropriate pin muxing.
The following is an example of the pin muxing of the UART1 device in
imx8mp-phyboard-pollux.dtsi
:
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD_UART1_DCE_RX
0x49
MX8MP_IOMUXC_UART1_TXD_UART1_DCE_TX
0x49
>;
};
The first part of the string MX8MP_IOMUXC_UART1_RXD_UART1_DCE_RX names the pad (in this example
UART1_RXD
). The second part of the string (
UART1_DCE_RX
) is the desired muxing option for this pad. The pad
setting value (hex value on the right) defines different modes of the pad, for example, if internal pull resistors are
activated or not. In this case, the internal resistors are disabled.
