10.
Circuit Diagrams and PWB Layouts
PNX85500 Control
1
8
770_504_10011
8
.ep
s
10011
8
PNX
8
5500 Control
B01E
B01E
2009-10-22
3
8
204 000
8
994
TUNER, HDMI & CI
D
C
S
W
HOLD
V
SS
Q
VCC
S
CL
ADR
0
1
2
S
DA
WC
IF5
3
B
3
IF54 C
3
DEBUG / R
S
2
3
2 INTERFACE
S
CL
FOR
FF29 C4
FF55 E
3
FF56 E
3
S
HIFTED
UP
FF66 F4
IF50 B
3
IF51 B1
IF52 B
3
DEBUG
3
F6
3
E5
3
F64 F5
3
F65 F5
IF55 C6
IF56 C7
IF57 C7
IF5
8
D2
IF59 E1
IF61 C4
IF62 C4
7F54-2 C7
7F5
8
D1
9CH0 C7
FF04 C4
DEBUG ONLY
S
DA
U
S
E ONLY
1F52 D
8
FF57 E2
FF5
8
C7
FF61 D4
FF62 D7
FF6
3
E4
FF64 F7
FF65 F4
3
F5
8
E1
3
F59 E
3
3
F60 E
3
3
F62 D5
A
B
C
D
E
F
A
3
F66 B7
3
F67 B6
3
F6
8
C7
3
F69 D7
7F52 B2
7F5
3
B7
7F54-1 C7
D
E
F
1F51 F
8
LEVEL
MAIN NVM
B
C
2F52 B1
2F5
3
D6
2F5
8
D2
3
F51 B1
3
F52 B
3
3
F5
3
C6
3
F54 D7
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
3
F54
FF66
RE
S
1K0
FF57
IF50
2F52
100n
IF55
RE
S
5
3
4
IF56
BC
8
47BPN(COL)
7F54-2
RE
S
FF62
1F51
1
2
3
4
5
6
7
10K
3
F5
8
RE
S
9CH0
IF51
IF57
100R
3
F62
3
F64
100R
FF61
+5V
+
3
V
3
-
S
TANDBY
7
2
1
8
4
3
Φ
512K
FLA
S
H
M25P05-AVMN6
7F52
6
5
RE
S
3
F6
8
47K
FF5
8
100R
3
F59
IF61
10K
RE
S
3
F69
FF04
PDTA114EU
RE
S
7F5
3
IF59
+
3
V
3
FF64
100R
3
F60
10K
3
F51
1
2
3
4
5
1F52
+
3
V
3
IF52
+
3
V
3
RE
S
+
3
V
3
-
S
TANDBY
100n
2F5
8
IF54
RE
S
2
6
1
FF65
BC
8
47BPN(COL)
7F54-1
2
3
6
5
8
4
7
7F5
8
EEPROM
Φ
(
8
K×
8
)
1
+
3
V
3
3
F5
3
10K
IF5
3
3
F66
10K
+
3
V
3
-
S
TANDBY
RE
S
RE
S
3
F67
10K
2F5
3
1
u
0
RE
S
+
3
V
3
-
S
TANDBY
FF6
3
3
F6
3
FF56
FF55
100R
3
F52
10K
IF5
8
FF29
3
F65
100R
IF62
BOO
S
T-PWM
BACKLIGHT-BOO
S
T
S
DM
S
PI-PROG
RE
S
ET-
S
TBYn
S
PI-PROG
S
DA-UP-MIP
S
S
CL-UP-MIP
S
S
CL-
SS
B
S
DA-
SS
B
TXD-UP
RXD-UP
PNX-
S
PI-CLK
PNX-
S
PI-
S
DO
PNX-
S
PI-C
S
Bn
PNX-
S
PI-
S
DI
PNX-
S
PI-WPn