Philips Semiconductors
UM10016_3
ISP1581 Hi-Speed USB MPEG2 Encoder Reference Kit
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual
Rev. 03.00 — 12 April 2004
14 of 28
7. Hardware Description
This section briefly describes the hardware implementation of the MPEG2 encoder with
Hi-Speed USB solution in terms of functions and connections between various interfaces. A
functional block diagram of the reference design is given in Figure 7-1.
MPEG2
Encoder
Video Decoder
Audio Decoder
CPLD
ISP1581
P87C54S
I
2
C-Bus
I
2
C Slave
I
2
C Slave
I
2
C Master
YUV4.2.0/YUV4.2.2
S-Video
Input
Composite
Video Input
PS Stream
I
2
S
High-Speed USB
Analog Audio
Input
Video
Input
Figure 7-1: Functional Block Diagram of the USB MPEG2 Encoder Reference Kit
7.1. Video-Input
Interface
The video-input interface consists of two analog inputs to connect Composite Video Bit Steam
(CVBS) and Luminance Chrominance (YC) sources to the board. A video-input processor (VIP)
SAA7114 is used on the board for video decoding and analog-to-digital conversion.
7.2. Analog Audio-Input Interface
The serial audio I
2
S ports are implemented on the board. These port can be provided with an
analog input source, using the audio bit-stream analog-to-digital converter DA1361TS for
generating the I
2
S signal.
7.3. MPEG Stream (PS Stream) Output Interface
The MPEG stream output port connects the SAA6752HS multiplexer to USB through a Complex
Programmable Logic Device (CPLD). The MPEG stream is set to the Data Expansion Bus
Interface (DEBI) slave mode. The output format is TTL. This interface also includes the data
request signal as SAA6752HS input and the data validated signal as SAA6752HS output.
7.4. I
2
C-Bus Interface
The P87C52X2 MCU is a bus master. It relays all I
2
C-Bus commands from the host to different
components on the board through the control pipe.
