M12L64164A IC Specification
SDRAM
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6
μ
s refresh interval
ORDERING INFORMATION
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE Comments
M12L64164A-5TG
200MHz
TSOP II
Pb-free
M12L64164A-6TG
166MHz
TSOP II
Pb-free
M12L64164A-7TG
143MHz
TSOP II
Pb-free
GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
S SQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
S SQ
DQ7
V
DD
LDQM
W E
CAS
RAS
CS
A
13
A
12
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
S SQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
N C
UD Q M
CLK
CKE
N C
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
15-4
15-4
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
N
O
I
T
C
N
U
F
T
U
P
N
I
E
M
A
N
N
I
P
CLK
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
A12 , A13
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
L(U)DQM
Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
VDD / VSS
Power Supply / Ground
Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC
No Connection
This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
C
on
tro
l L
og
ic
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decod
er
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Lat
ch Cir
cuit
Input & Out
put
Buf
fer
Address
Clock
Generator
CLK
CKE
Command Dec
oder
CS
RAS
CAS
WE
