Philips FW-V720, Service Manual, Page: 44 / 102

NOTES:
8-2 8-2
Brief Introduction on the MPEG
1. When VCD source is selected the MPEG_RESET line will go positive triggering the following:
- DRST pulse to reset 8-bit microcontroller IC 7212 P83C528EBB
- RSTOUT# pulse to reset IC 7201 ESS3880
- IC7212 sends CD10_RST to reset Signal Processor IC 7802 on the in the VCD electronics.
2. Communication will establish as follows:
- DSA_ACK, DSA_STB and DSA_DAT between
µ
Processor IC 7401 on the Front Board and IC 7201 ESS3880.
- DSA_STB to IC7204 ESS3883 to select between NTSC (Lo) or PALS (Hi)
- DSA_A, DSA_D and DSA_S between IC 7201 ESS3880 and microcontroller IC7212
- SILD, SICL, RAB and SDA between microcontroller IC7212 P83C528EBB and Signal Processor IC7802 SAA7327H/
M2B on the CD Board.
3. Other activities between IC7201 ESS3880 and Eprom IC7202, Dram IC7203 and IC7204 ESS3883 will follows resulting in
the OSD display on the TV set connected to the Video out socket.
4. When play button is activated the I 2 S signal (IIS_SCLK, IIS_WCLK and IIS_DATA) from the CD Board will enter IC7201
ESS3880 which will work closely with the Eprom IC7202 and Dram IC7203. Inverter IC7205 74HC04D serves to reconstruct
the Digital signal & level required by IC7201 ESS3880.
5. Digital Audio information (AUDIOCLK, AUDATA and BCLK) will be send to DAC (Digital to Analog Converter) of IC7204
ESS3883.
6. Analog output (AOL+, AOL-, AOR+ and AOR-) is amplified by the differential Op. Amplifier IC7207 NJM4560M.
7. Digital Video information YUV(0….7) will be send to the Video processing part of IC7204 ESS3883 and out to the Video out
socket.
8. The HSYNC & VSYNC from IC7204 ESS3883 to IC7201 ESS3880 are to synchronize the Digital Video Information.
9. Mic Echo Input into IC7204 ESS3883 is converted to digital signal (ARCLK, AIN and ARFS) for IC7201 ESS3880 to combine
into the Digital Audio Information.
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