Philips Expanium AZ 5150, Service Manual, Page: 16 / 32

4 - 4 4 - 4
VIDEO-TIMING
CONTROLLER
SUB-CARRIER
GENERATION
SINE-TABLE
SERIAL
TO
PARALLEL
4:2:2 to
4:4:4
INTER-
u-FILTER
v-FILTER
y-FILTER
POLATION
H, V-SYNC
CLK_27
SLEEP
P[7:0]
MODE[3:0]
SVIDEO
MASTER
CBSWAP
COLOR-BURST
&
MODULATION
&
MIXER CVBS/Y
CVBS/C
DAC-
MAPPING
VBIAS VREF_O FSADJUST COMP
Name I/O Pin Description
CLKI I 29 Pixel clock, 27MHz, twice the Y sample rate
VSYNC I/O 32 Vertical sync, output in master mode or input in slave mode, is
synchronized by CLK.
HSYNC I/O 1 Horizontal sync, output in master mode or input in slave mode, is
synchronized by CLK too.
P[7:0] I 28-21 YCbCr pixel inputs (TTL compatible). Also, synchronized by CLK with
respect to the incoming HSYNC timing, the higher index corresponds
to a greater significance.
MD[3:0] I 17-20 Configuration inputs
MASTER I 16 in 0: slave mode, h and v sync are inputs. 1: master mode, h and v
sync are outputs.
CBSWAP I 15 0: normal Cr, Cb sequence. 1: swaps Cr, Cb sequence
SVIDEO I 14 0: composite output same signal on both Y, C channels, 1: s-video
output, Y, C channels.
SLEEP I 13 1: power down, reset 0: normal operation
FSADJUST I 5 Full scale adjust control pin. A resistor is connected to GND. Used to
control the full-scale output current on analog outputs.
COMP I 6 Compensation pin. A 0.1 F capacitor is used to bypass this pin to
VCC.
VREFO I 8 Voltage reference output, typically 1.2V, may be used to connect to
VREFI input.
VREFI/
VRDAC I 9 Voltage reference input, typically 1.235V. A 0.11 F capacitor must be
used to decouple this input to GND. DAC current switch reference
input, connect to VREFO output.
VBIAS O 10 DAC bias voltage, 0.7 v less than COMP signal
CVBS/C O 11 Composite output or chrominance
CVBS/Y O 4 Composite output or luminance (with blanking and sync)
VAA 7 Analog power
VDD 31 Digital power
GND 30 Digital ground
AGND 3, 12 Analog ground
NC 2 No connection
BLOCK DIAGRAM OF INTEGRATED CIRCUIT PINS DESCRIPTION OF INTEGRATED CIRCUIT
CS8552
CS8552