Philips DVDR3305/02 Service Manual Download Page 4

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EN 4

3139 785 3093x

Technical Speci

cations and Connection Facilities

1.6.2 Scart

Audio

Output voltage 2 channel mode

: 1.6Vrms ± 2dB

Channel unbalance (1kHz)

: < 1dB

Crosstalk 1kHz

: > 85dB

Crosstalk 16Hz-20kHz

: > 70dB

Frequency response 20Hz-20kHz : ± 0.2dB max

Signal to noise ratio

: > 80dB

Dynamic range 1kHz

: > 75dB

Distortion and noise 1kHz

: > 75dB

Distortion and noise 16Hz-20kHz : > 50dB

Intermodulation distortion

: > 70dB

Mute

: > 80dB

Outband attenuation:

: > 40dB above 25kHz

1.7 Digital

Output

1.7.1 Coaxial

CDDA / LPCM (incl MPEG1)

: according IEC958,

IEC60958-1,-3

MPEG2, AC3 audio

: according IEC1937,

IEC61937

DTS

: according IEC1937,

IEC

61937

amendment

1.8

Digital Video Input (IEEE 1394)

1.8.1 Applicable

Standards

Implementation

according:

IEEE Std 1394-1995

IEC 61883 - Part 1

IEC 61883 - Part 2 SD-DVCR (02-01-1997)

Speci

cation of consumer use digital VCR’s using 6.3 mm

magnetic tape - dec. 1994

Annex A of 61883-1

1.9

Dimensions and Weight

Height of feet

: 5.5mm

Apparatus tray closed

: WxDxH:435x285x65mm

Apparatus tray open

: WxDxH:435x422x65mm

Weight without packaging

: app. 4.0kg ± 0.5kg

Weight with packaging

: app. 6kg

1.10 Laser Output Power & Wavelength

1.10.1 DVD

Output power during reading

: 0.8mW

Output power during writing

: 20mW

Wavelength

660nm

1.10.2 CD

Output power

: 0.3mW

Wavelength

780nm

Summary of Contents for DVDR3305/02

Page 1: ...Layout Analog Main Part Top View 33 Layout Analog Main Part Bottom View 34 Front Front Panel 35 Contents Page Front Front Panel 36 Layout Front Panel Top View 37 Front Standby 38 Layout Standby Top View 38 Digital Back end Processor 39 Digital Memory 40 Digital IEEE 1394 Physical Layer 41 Digital Video Input Processor 42 Digital Interfaces 43 Layout Digital Main Part Top View 44 Layout Digital Mai...

Page 2: ...y at 40dB S N 60dBμV at 75 Ω video unweighted 1 3 4 Video Performance Channel 25 503 25 MHz Test pattern PAL BG PHILIPS standard test pattern RF Level 74dBV Measured on SCART 1 Frequency response 0 1 4 00 MHz 3dB Group delay 0 1 MHz 4 4 MHz 0 nsec 150 nsec 1 3 5 Audio Performance Audio Performance Analogue HiFi Frequency response at SCART 1 L R output 100 Hz 12 kHz 0 3dB S N according to DIN 45405...

Page 3: ...75Ω 20 CVBS in 21 Shield for 100 white 1 4 3 Audio Video Front Input Connectors Audio Cinch Input voltage 2 2Vrms Input impedance 10kΩ Video Cinch Input voltage 1Vpp 3dB Input impedance 75Ω Video YC Hosiden According to IEC 933 5 Superimposed DC level on pin 4 load 100kΩ 2 4V is detected as 4 3 aspect ratio 3 5V is detected as 16 9 aspect ratio Input voltage Y 1Vpp 3dB Input impedance Y 75Ω Input ...

Page 4: ...8 1 3 MPEG2 AC3 audio according IEC1937 IEC61937 DTS according IEC1937 IEC 61937 amendment 1 1 8 Digital Video Input IEEE 1394 1 8 1 Applicable Standards Implementation according IEEE Std 1394 1995 IEC 61883 Part 1 IEC 61883 Part 2 SD DVCR 02 01 1997 Specification of consumer use digital VCR s using 6 3 mm magnetic tape dec 1994 Annex A of 61883 1 1 9 Dimensions and Weight Height of feet 5 5mm App...

Page 5: ...nts and tools at this same potential Available ESD protection equipment Complete kit ESD3 small tablemat wristband connection box extension cable and earth cable 4822 310 10671 Wristband tester 4822 344 13999 Be careful during measurements in the live voltage section The primary side of the power supply including the heatsink carries live mains voltage when you connect the player to the mains even...

Page 6: ... be able o To reach at least a solder temperature of 400 C o To stabilize the adjusted temperature at the solder tip o To exchange solder tips for different applications Adjust your solder tool so that a temperature around 360 C 380 C is reached and stabilized at the solder joint Heating time of the solder joint should not exceed 4 sec Avoid temperatures above 400 C otherwise wear out of tips will...

Page 7: ...faultSubtitleLanguage OnScreenDisplayLanguage English DefaultAudioLanguage English English English System Menu Clock Time hh mm ss ShowDivX RegistrationCode Date dd mm yy 31 01 05 10 33 57 OK SortChannel Sort ChannelSearch System Menu General VideoOutputFormat ScreenSaver On RestoreFactorySettingd Germany PAL OK Country 3a Press STANDBY ON 2 on the DVD recorder to turn it on Note For successful in...

Page 8: ...led FRONT A V IN or VIDEO Choose the different modes using TV remote control Or use theTV remote control to select Channel 1 onTV then press Channel down button until you get the picture See your TV manual for more details 4a Insert a recordable DVD R RW with the label facing up 4b To record TV programme press REC SOURCE to select Tuner To record from an external device connected to this DVD Recor...

Page 9: ...s screw driver and push the lever in the direction as shown in Figure 4 1 to unlock the tray before sliding it out Figure 4 1 2 Remove the Tray Cover as shown in Figure 4 2 Figure 4 2 4 1 2 Dismantling of the Front Panel Assembly 1 Remove the 3 screws 188 and release the 2 snap hooks on the side before removing the front assembly 1 Figure 4 3 2 Remove the 5 screws 186 to remove the front plate 184...

Page 10: ...he basic engine to the vertical position Figure 4 6 4 1 4 Dismantling of the Digital Board 1 Remove the 4 screws 272 to loose the Digital Board as shown in Figure 4 7 4 4 Figure 4 7 2 Service Position can be achieved by flipping the Digital board to the Vertical Position as shown in Figure 4 8 Figure 4 8 Note The cable just to transfer the service connection to the analog board from socket 1101 ca...

Page 11: ...crews 244 and 4 screws 252 and screw 230 2 Remove 4 screws 270 and 3 screws 268 3 Service Position can be achieved by flipping the analog board to the Vertical Position as shown in Figure 4 9 Figure 4 9 Note Please cover the Live Area during trouble shooting Figure 4 10 Figure 4 10 Figure Live Area ...

Page 12: ...ding process is successful the tray will open and the TV connected to the set will display System is successfully upgraded Remove disc from tray reset system 7 Remove the Upgrade Disc and press OK button on Remote control to confirm 8 The TV screen goes blank and the Philips Logo screen appear again after the tray door has closed C How to Restore Factory setting Default setting 1 Power up the set ...

Page 13: ...EN 13 3139 785 3093x 5 Upgrade Software Repair Chart 5 2 Repair Chart 5 2 1 Completely Dead Set ...

Page 14: ...EN 14 3139 785 3093x 5 Upgrade Software Repair Chart 5 2 2 Cannot Read Disk 5 2 3 Disk Unknown ...

Page 15: ...EN 15 3139 785 3093x 5 Upgrade Software Repair Chart 5 2 4 Audio No Sound Playback ...

Page 16: ...EN 16 3139 785 3093x 5 Upgrade Software Repair Chart 5 2 5 Audio No Sound TV External Source ...

Page 17: ...EN 17 3139 785 3093x 5 Upgrade Software Repair Chart 5 2 6 No Video Out Upon Power ON Assume set is not dead ...

Page 18: ...EN 18 3139 785 3093x 5 Upgrade Software Repair Chart 5 2 7 No Video In Only 5 2 8 Tuner Not Functioning ...

Page 19: ...GITAL AUDIO RS232 SERVICE 1111 1522 1551 DIG VIDEO 21 20 18 2 16 7 1 3 5 7 9 RF IN ANTENNA RF OUT TV PHY F438 DIGITAL AUDIO OUT DOMINO DMN 8602 MPEG 2 AC3 CODEC EEPROM DIGITAL AUDIO I2C A_PCMCLK A_xCLK BUFFER A_YCVBS DAC D_DATA0 D_WCLK D_BCLK 9 11 12 14 D_PCMCLK D_xCLK ANALOG VIDEO 1800 POWER SUPPLY PSU 5N GND 5V GND GND 12V GND 3V3 3V3 3V3 3V3 1403 1 12 5V GND ION 5V GND GND 12V GND 3V3 3V3 3V3 3...

Page 20: ...Processor NEC uPD 16316GBT Audio Switches HEF4052B Fan 1 Reset Multi Sound Processor MSP34x5 1 KILL Supply VFT Display Power Supply RC Front Keys DIGITAL BOARD DIMENSION DVDR D_KILL AIN_SEL0 AIN_SEL1 IDE0 HOST_Reset I2C 5V INT I2C 3V3 Reset 5VSTBY 2 2 2 1 1 35 STBY POWER_FAIL BKILL 1 KILL AKILL RSA1 RSA2 FRONT Board FAN_CTRL Control Block Diagram ...

Page 21: ... 4 GND 1 3V3 1 GND 1 GND 30 VIA_GY 1 RESETn 1 RESETn 2 3V3 2 BCKI 2 SCL0 29 GNDV 2 GND 2 GND STDBY KEY 3 3V3 3 WCKI 3 SDA0 28 VIA_BPb 3 DD 7 3 DD 7 0100 4 3V3 4 GND 4 RDY_FM 27 GNDV 4 DD 8 4 DD 8 1 KEY1 5 GND 5 DAI 0 5 D_FM 26 VIA_RPr 5 DD 6 5 DD 6 2 KEY2 6 12V 6 GND 6 D_HOST 25 GNDV 6 DD 9 6 DD 9 7 GND 7 MCKI 7 GND 24 24 VIA_SY_FR 7 DD 5 7 DD 5 8 GND 8 GND 8 FPSCK 23 23 GNDV 8 DD 10 8 DD 10 9 5V ...

Page 22: ...07 ROUT F209 YCVBS_OUT1 F417 VDrain No Disc F417 Vdrain Standby F602 CVBS F604 Y_OUT F605 C_OUT I303 AFER I304 AFEL I310 ARADC I311 ALADC I315 AOUT1L I317 AOUT1R I407 Vgate No Disc I407 Vgate Standby I409 VSource No Disc I409 VSource Standby I906 Tstpoint 7500MSP XTAL IN 7500MSP XTAL OUT I110 SIFOUT I719 ALDAC I721 ARDAC ...

Page 23: ...rms of Digital Board IC 7211 PIN 45 IC 7211 PIN 46 IC 7401 PIN74 IC 7401 PIN75 T121 T122 T351 IC7301 PIN 42 T352 IC 7301 PIN 43 T525 T526 T529 CVBS_TU CVBS_RE CVBS_FR T527 T531 T535 SY_RE SY_FR CY T528 T530 SC_RE SC_FR T532 BPr T533 BPb T537 BCK T538 WCK T539 DA T540 MCK ...

Page 24: ...EN 24 3139 785 3093x 6 Block Diagrams Waveforms Wiring Diagram Test Points Overview for Analog Board Analog Board TestPoint pdf 2005 07 15 ...

Page 25: ...EN 25 3139 785 3093x Test Points Overview for Digital Board 6 Block Diagrams Waveforms Wiring Diagram Digital Board TestPoint pdf 2005 07 15 ...

Page 26: ...2107 G3 2108 G3 2109 H5 2110 H5 2145 F5 3100 C4 2 0 1 5 0803 5VSTBY 5V 5V_FV BARCODE I110 u 2 2 5 4 1 2 5V 33VSTBY V 5 2 5V_FV 0 0 1 2 V 3 6 u 7 4 I109 I108 BC857BW 7100 n 0 0 1 7 0 1 2 5V_FV n 2 2 3 0 1 2 I103 4 0 1 2 V 0 5 7 u 4 5V_FV 2 0 1 2 n 0 0 1 5103 n 0 1 5 0 1 2 c710 GND_TU 0 1 1 2 p 7 4 p 7 4 9 0 1 2 K 7 4 3 0 1 3 I100 I101 5V 1 0 1 5 u 0 1 1 0 1 2 n 0 1 6 0 1 2 n 0 1 I106 5104 8 0 1 2 R...

Page 27: ...1 3 1 2 3 5 1 2 2 n 0 0 1 5VSTBY 2 5 2 3 K 0 1 2218 1u0 2234 1u0 5 6 7 8 9 9 1 2 0 2 1 2 2 2 3 2 4 2 3 4 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 4 0 2 1 A K R T B N M F 4 2 1 1 2 F 1 5 2 3 0 K 1 I214 9161 R 0 5 1 0 6 2 3 3259 150R I219 2226 1u0 5 1 2 6 2 1 C 4 8 3 X Z B K 0 1 3 5 2 3 I203 5NESD 2 0 2 F 9 3 2 F 5V 33 100n 2232 0 2 4 2 0 3 2 3 6 3 7 19 1 41 25 21 9 3 15 10 29 17 9 31 37 38 8 44 2 14 1...

Page 28: ...to IOV from CU 2300 1u0 4 0 3 3 K 0 0 1 8 1 3 2 p 0 0 1 0 1 3 2 0 n 1 I308 1 2 3 2 V 3 6 u 7 4 I303 1 0 3 3 K 0 0 1 5NSTBY V 3 6 u 7 4 0 2 3 2 6 1 3 I 5VSTBY I304 3 2 3 3 K 0 1 2301 1u0 2302 1u0 5VSTBY 5VSTBY 3 1 3 I 1u0 2307 I315 1u0 2304 2312 100n 2309 1u0 2 1 8 4 5VSTBY MC33078D 7300 1 3 7301 1 MC33078D 3 2 1 8 4 I305 R 0 2 8 9 1 3 3 I318 5 6 7 8 4 7300 2 MC33078D 1u0 2303 7305 BC817 25W I306 B...

Page 29: ...OT 12VSTBY I400 2 0 4 5 I401 GNDHOT 12VE Y B T S V 8 3419 470R STP16NF06FP 7413 0 n 1 5N 12V 6 0 4 2 1u0 4 6 U 7418 BC337 25 2408 GND 1 2 2 0 4 I 1400 B2P3 VH u 2 2 2 3 4 2 3476 10K GND 1 6 4 3 9 K 3 3434 K 7 4 SB340 6410 7 6 U 4 0 4 7 2 A 1 K 3 R 9403 Z C A 1 3 4 L T 7410 PDTC124EU n 0 0 1 I440 4 3 4 2 5 2 4 2 u 0 6 5 I445 6402 1N4006 2402 1n0 F421 K 0 1 0 7 4 3 5Vreg 7 3 4 2 V 0 5 2 u 2 18K 5406...

Page 30: ... 2 0 n 1 5 1 5 I 7 1 5 2 0 n 1 3 1 5 2 n 0 0 1 V 0 5 7 u 4 9 1 5 2 1u0 2505 I501 0 0 5 2 V 5 2 u 0 1 2 1 5 I 3 1 5 I PDTC124EU 7501 P T 9 2 1 F E R V 5 2 2 F E R V 2 4 P O T F E R V 5 N I _ L A T X 6 T U O _ L A T X I504 41 SC1_IN_R 31 SC1_OUT_L 30 SC1_OUT_R 37 SC2_IN_L 38 SC2_IN_R 11 STBYQ 4 N E T S E T 7 I2S_DA_OUT 15 I2S_WS 43 MONO_IN 3 2 4 2 8 2 2 3 22 RESETQ 40 SC1_IN_L DVSUP 9 0 O I _ R T C ...

Page 31: ...13 u 0 1 1 0 7 5 I712 0 2 7 3 9 K 3 12VSTBY 3722 4K7 F704 n 0 0 1 1 2 7 2 I704 A n 0 0 1 I711 8 0 7 2 6 3V 47u 2706 GND I722 A D N G I718 F712 A p 3 3 4 0 7 2 3V3SW 5VSTBY A 50V 10u 2727 BC847BW 7706 I715 3V3SW K 0 1 5NSTBY 10u 5700 7 1 7 3 3731 100K I716 n 2 2 9 1 7 2 1 0 7 3 K 2 2 A GND 4700 6 3 7 3 K 2 2 5VSTBY I701 5VSTBY GND 5NSTBY D N G 5NSTBY I713 I708 6701 BAS316 K 7 2 7 2 7 3 D N G A I702...

Page 32: ... 1900 C9 1901 D9 2900 A4 2901 A4 2902 D2 2903 E4 2904 D5 2905 D7 2906 D8 2907 F8 3900 C2 3901 B3 3902 B4 10K 3902 F907 F905 R 0 6 5 0 0 9 3 F906 F901 I903 GND 3 1 IN 2 VS JFJ1000 6900 I908 5V I905 5V R 0 7 4 2 1 8 4 7 0 9 2 V 5 2 n 0 0 1 I901 1 2 3 4 6 6RG 7901 I906 BRACKET 0007 4 0 9 I I907 I902 14 12 470R 3908 74HCU04D 7900 6 13 7 1900 1 2 3 4 1K0 3913 310360100162 3911 75R 2904 7 14 10 100n 74H...

Page 33: ...EN 33 3139 785 3093x 7 Circuit Diagrams and PWB Layouts Layout Analog Main Part Top View Analog_Topview_3355_02 pdf 2005 07 15 ...

Page 34: ...EN 34 3139 785 3093x 7 Circuit Diagrams and PWB Layouts Layout Analog Main Part Bottom View Analog_Bottomview_3355_02 pdf 2005 07 15 ...

Page 35: ...9 3132 2K7 3104 330R 0 K 1 6 0 1 3 2101 220n 6K8 3101 560R 3128 F118 3111 10R GND EVQ11L05R 1208 GND 1215 F128 EVQ11L05R F123 F125 EVQ11L05R 1207 3102 33R 1102 1 GND u 0 0 1 BC847BW 7100 GND 5100 BC847BW 7106 K 0 1 8 0 1 3 9 0 1 3 R 0 7 4 3 0 1 4 GND I108 F110 2115 V 3 6 0 m 1 F104 BC327 25 7103 11 7 14 10 7104 5 74HCT14D n 0 0 1 0 0 1 2 3135 100R F132 I103 4 2 1 2 p 2 2 p 2 2 3 2 1 2 1101 32K768 ...

Page 36: ...7 2 0 2 3 8 0 2 2 p 0 0 1 GND 7 0 2 2 GND p 0 0 1 2206 470p 6 0 2 3 R 5 7 n 0 0 1 GND 4 0 2 2 GND 1 0 2 3 R 5 7 GND GND GND 470R D N G F206 3204 GND F205 6 F212 1 3 2 5 4 1 0 2 6 2 1 C 4 8 3 X Z B JPJ1127 01 0020 1301 9 0 2 2 2 1 C 4 8 3 X Z B 0 0 2 6 GND n 0 0 1 0 0 2 2 n 0 0 1 F208 3200 10K F200 GND F201 470p F207 4 2205 S4B PH K 1401 1 2 3 5401 042 101 92 1 2 3 4 1402 3205 470R GND GND F204 GND...

Page 37: ...EN 37 3139 785 3093x 7 Circuit Diagrams and PWB Layouts Layout Front Panel Top View FrontPanel_Topview_31947_3355 pdf 2005 07 15 ...

Page 38: ...D2 6300 D2 6301 D3 F300 C2 F301 C2 I300 C4 DC0 4 2 D A B E 1302 C2 E C A B C D I300 1303 F301 EVQ11L05R 0 0 3 2 GND F300 2 n 2 0 0 3 6 8 V 6 C 4 8 3 X Z B 1 2 8 V 6 C 4 8 3 X Z B 1 0 3 6 S2B EH 1302 3139 243 32017 2005 04 12 Layout Standby Top View FrontPanel_Topview_hmc1_32017_3355_02 pdf 2005 07 15 ...

Page 39: ... 3147 T101 1 1K2 3191 4 5 7 47R 3173 4 3173 2 47R 2 n 0 0 1 6 5 1 2 T102 T106 n 0 0 1 9 2 1 2 3161 10K Y1 N3 M4 M3 M2 N2 U3 R2 T2 W1 V2 T3 T1 R3 P1 P3 R1 R4 U1 W2 P4 P2 N4 ATAPI Φ V3 T4 V1 U2 U4 3 6 7101 6 DMN 8602 3172 3 47R 2K2 2K2 3149 3151 7 3155 2K2 3183 2 22R 2 A12 A17 B15 B16 B17 A14 B13 A13 A15 B14 Φ C14 D14 D13 C13 A16 n 0 0 1 7 4 1 2 AUDIO DMN 8602 7101 2 3 6 22R 3183 3 K 0 1 4 0 1 3 3 0...

Page 40: ...8 4 6 6 6 2 1 2 5 8 5 4 6 21 51 1 8 1 3 3 3 9 5 1 5 5 1 6 49 16 14 17 19 25 43 50 53 23 47 63 65 5 7 8 10 11 13 54 56 20 45 44 46 24 2 4 57 59 60 62 31 32 35 36 37 38 39 40 26 27 22 16Mx16 SDRAM 29 30 28 41 42 n 0 0 1 7231 DDR Φ 2 0 2 2 2257 100n 2 7 1 8 3267 2 47R 5 3263 1 47R 3269 4 47R 4 3277 4 47R 4 5 4 5 3281 4 47R 100n 2275 47R 3257 4 4 5 3257 3 47R 3 6 4 5 3273 4 47R 2215 100n 2272 100n 1 8...

Page 41: ... E5 3360 E5 3361 E5 3362 E5 4361 E5 5301 C6 7301 D6 T301 E7 T302 E7 T303 E7 F G H I A B C 2306 D7 1K0 3301 T304 T352 T301 4K7 3310 2 2 7 3310 3 4K7 3 6 4K7 3310 4 4 5 1K0 3362 100n 25V 10u 2301 2307 100n 2305 100n 2304 100n 2302 2351 2352 33p 33p 680R T316 3306 4361 T314 3304 10K T311 T310 2 4 3 3 1 R 6 5 T307 7 K 4 2 2 3 3 T351 10K 3303 3302 10K 2306 100n 1 R 6 5 1 4 3 3 680R 3307 1K0 3361 100R 3...

Page 42: ... F5 3480 F5 3481 E11 3482 E11 3484 F11 3486 F11 3488 1 F11 4475 E6 4476 E5 4477 E6 4478 E6 4479 E5 4480 E6 4481 E11 4486 E11 5401 C2 5411 D2 5421 D2 5431 E2 7401 C7 F401 D10 F402 D10 T400 E10 T401 F10 T402 F10 600R 270R 4479 4475 600R 4478 1 R 5 7 6 7 4 3 1 R 5 7 1 7 4 3 T411 100n 2479 T407 T409 T405 T408 T406 52 51 50 47 46 45 44 43 8 9 16 17 18 23 73 74 75 54 53 1 6 7 7 6 7 33 34 28 29 80 1 2 7 ...

Page 43: ...2 n 0 0 1 9 1 5 2 5518 BLM31 1 1 5 2 V 6 1 u 0 3 3 u 0 2 2 8 1 5 2 1 2 5 2 V 6 1 u 0 2 2 V 6 1 3 6 T607 3574 3 33R T605 T608 T606 1 2 3 4 B4B PH K 1502 T555 2571 22p 22p 2570 T527 n 0 0 1 0 2 5 2 2 0 5 6 0 6 7 T A B 0 6 7 T A B 1 0 5 6 T562 3506 T561 15K 7 T509 T565 33R 3574 2 2 3574 1 33R 1 8 22p 2596 T502 T503 T501 22R 3557 T569 p 2 2 2 5 5 2 T510 T522 T615 3563 22R p 2 2 2 6 5 2 n 0 0 1 7 1 5 2...

Page 44: ...EN 44 3139 785 3093x 7 Circuit Diagrams and PWB Layouts Layout Digital Main Part Top View Digital_Topview_3355_02 pdf 2005 07 15 ...

Page 45: ...EN 45 3139 785 3093x 7 Circuit Diagrams and PWB Layouts Layout Digital Main Part Bottom View Digital_Bottomview_3355_02 pdf 2005 07 15 ...

Page 46: ...EN 46 3139 785 3093x 7 Circuit Diagrams and PWB Layouts Notes ...

Page 47: ... 1 7 VFD Heater Voltage Generator The oscillator circuit provided by 5100 2101 2102 7100 provides the necessary sine wave signal for transistors 7101 7102 7103 to generate the 50 duty cycle 48KHz AC square wave signal for the filament of the VFD 8 1 8 Timer Wake up activation During the Standby mode the slave μP provides a wakeup call POWER_CTL line switches to high to the Domino Host on the Digit...

Page 48: ...te video processing is done in this unit and the video output CVBS is taken out from the VID_OUT pin via a transistor as CVBS_TV line to the Video I O circuitry The audio IF component SIF1 is taken out from the SIFOUT pin for the demodulation by the Multi sound processor MSP Audio demodulator The sound demodulation is done by the MSP3415 7500 which is also fully controlled via I2 C bus by the Domi...

Page 49: ...ig board 3 ALADC ARADC 15 CS4351 DAC VOR VOL 18 ARDAC ALDAC D_DATA from dig board LH Logic 1 3 5 1 10 9 LL HL MSB LSB HEF4052 4 5 15 L H L H HH LH LL HL HH 3 1 11 14 12 13 2 6 MSB LSB POS 7302 MSP3415G 2 I2C Control 8 9 12 13 26 27 31 30 37 38 41 40 Q Peak Det Source select Demodulator DACM_L DACM_R SC1_OUT_L SC1_OUT_R POS 7500 0dB 0dB LH Logic 1 3 5 1 10 9 LL HL MSB LSB HEF4052 2 4 12 L H L H HH ...

Page 50: ...t AIN2L AIN2R Front Cinch AINFL AINFR or the MSP AFEL AFER and routes to the audio ADC ALADC ARADC for record purposes The switch is controlled via RSA1 and RSA2 signals coming from the MSP 8 2 6 Audio ADC DAC The conversion of analog audio signals from the record selector 7302 outputs ALADC ARADC is done via UDA1361TS 7704 This IC can process input signals up to 2Vrms by using external resistors ...

Page 51: ...AR D_CVBS D_Y D_C D_VR D_YG D_UB CVBS_TV D_Y D_CVBS A_UB A_YG VideoIn VideoOut R C_Out G Bout Cin FastBlk SlowBlk D_CVBS D_Y CVBS Y C A_UB A_YG A_VR A_VR CRout ROUT CVBS_RE YCVBSOUT1 CVBSOUT2 GOUT BOUT FBOUT CVBS_TV CVBSIN1 YCVBSIN2 D_CVBS D_Y RCIN D_C GIN RCIN BIN D_YG D_VR D_UB FBIN CVBS_FIN Y_FIN C_FIN CVBS_TV FBIN to CU From CU DigOUT1 pin 42 0V 2 2V 5V Video Aspect Ratio detection AV switchin...

Page 52: ... Digital board The output signal CVBS_RE together with the other signals CVBS_FIN Y_FIN C_FIN from the Front and RCB from Scart2 are routed directly to the VIP on Digital board for further processing The signals D_C and D_Y are fed through 7606 6dB amplification and D_C via transistors 7213 7212 as driver to the S Video output socket Likewise the signal D_CVBS is fed through 7606 6dB amplification...

Page 53: ...t to Video Input Processor TVP5146P 7401 The digital video input signals from the DV in on the Front board are routed from connector 1521 via the IEEE 1394 PHY IC 7301 to the Domino chip 7101 The Video Input Processor encodes the analogue video to digital video stream CCIR656 format The output stream named VID_D 9 0 is then routed to the Domino chip This IC encodes and decodes the digital video st...

Page 54: ...Digital board DMN 8602 Basic Engine VAD8041 Delay t3 VIP TVP5146 Delay t2 PDI1394P25BD Delay t2 FLASH MEMORY POWER ON RESET LOW VOLTAGE DETECTION NCP303LSN30 IC7595 HOSTRST 5V Supply FRONT MICROPROCESSOR RSTn SYSRST LNK_RST VID_RST IDE_RST Figure 8 5 DOMINO_RESET 8 3 5 Power Supply The Digital board is not powered in standby mode The control signal STBY on the analog board will enable the PSU and ...

Page 55: ... mV clamp DRIVER START UP CURRENT SOURCE 0 75 V 0 5 V 5 Isense 6 DRIVER MGU230 4 DEM 8 DRAIN 7 HVS n c OCP LEB blank Iss 2 5 V burst detect Figure 8 6 PIN DESCRIPTION AND CONFIGURATION SYMBOL PIN DESCRIPTION VCC 1 supply voltage GND 2 ground CTRL 3 control input DEM 4 input from auxiliary winding for demagnetization timing OVP and OPP Isense 5 programmable current sense input DRIVER 6 gate driver ...

Page 56: ..._CL I2C_DA 13 12 10 43 37 38 40 41 39 21 17 2 3 18 ADR_CL I2S_WS XTAL_IN I2S_CL XTAL_OUT 14 15 5 6 AVSS 44 AHVSS AGNDC DVSS VREF1 VREF2 VREFTOP RESETQ STANDBYQ TESTEN TP 7 4 11 22 42 25 29 20 36 35 CAPL_M 34 DVSUP AVSUP AHVSUP 33 19 1 N C 23 24 28 32 N C N C N C De Modulator Pre processing Source select Pre processing ADC ADC Prescale SCART DSP input select Loud speaker sound proeessing Loud speak...

Page 57: ...8 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 Figure 8 8 IC7703 CS4351 192KHz Stereo DAC with 2vrms line out BLOCK DIAGRAM PCM Serial Interface Interpolation Filter with Volume Control Internal Voltage Reference External Mute Control DAC Serial Audio Input Left and Right Mute Controls 2 Vrms Line Level Right Channel Output 2 Vrms Line Level Left Channel Output Reset ...

Page 58: ...e VA_H 17 High Voltage Analog Power Input Positive power supply for the analog section VL 20 Serial Audio Interface Power Input Positive power for the serial audio interface BMUTEC AMUTEC 14 19 Mute Control Output Control signal for optional mute circuit AOUTB AOUTA 15 18 Analog Outputs Output The full scale analog line output level is specified in the Analog Characteris tics table Control Port De...

Page 59: ...VINL 1 left channel input Vref 2 reference voltage VINR 3 right channel input VRN 4 negative reference voltage VRP 5 positive reference voltage SFOR 6 data format selection input PWON 7 power control input SYSCLK 8 system clock 256 384 512 or 768fs VDDD 9 digital supply voltage VSSD 10 digital ground BCK 11 bit clock input output WS 12 word select input output DATAO 13 data output MSSEL 14 master ...

Page 60: ...k Interface I O Arbitration and Control State Machine Logic Bias Voltage and Current Generator Transmit Data Encoder Cable Port Crystal Oscillator PLL System and Clock Generator TPA CPS TPA TPB TPB XI XO FILTER0 FILTER1 LPS ISO CNA SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PC0 PC1 PC2 C LKON R0 R1 TPBIAS PD RESET CNA output is only available in the 64 pin PAP package Figure 8 11 ...

Page 61: ...AGND AVDD 36 35 34 33 32 31 30 29 28 27 26 25 16 1 2 3 4 5 6 7 8 9 10 11 12 SYSCLK CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PD 17 18 19 20 47 46 45 44 43 48 42 40 39 38 41 21 22 23 24 37 13 PHP PACKAGE TOP VIEW TSB41AB1 PLLGND PLLV FILTER1 FILTER0 LREQ DGND DGND DV TESTM SE SM C LKON PC1 PC2 ISO CPS DV RESET XO XI DGND LPS PC0 DD DV DD DD DD Figure 8 12 ...

Page 62: ...ven low except during hardware reset when it is high impedance The link on output is activated if the LLC is inactive LPS inactive or the LCtrl bit cleared and when a the PHY receives a link on PHY packet addressed to this node or b the PEI port event interrupt register bit is 1 or c any of the CTOI configuration time out interrupt CPSI cable power status interrupt or STOI state time out interrupt...

Page 63: ... is powered see Figure 9 A pulsed signal should be used when an isolation barrier exists between the LLC and PHY See Figure 10 The LPS input is considered inactive if it is sampled low by the PHY for more than 2 6 μs 128 SYSCLK cycles and is considered active otherwise that is asserted steady high or an oscillating signal with a low time less than 2 6 μs The LPS input must be high for at least 21 ...

Page 64: ...t This input is used in manufacturing test of the TSB41AB1 For normal use this terminal should be tied to GND 1 CMOS O System clock output Provides a 49 152 MHz clock signal synchronized with data transfers to the LLC 22 CMOS I Test control input This input is used in manufacturing test of the TSB41AB1 For normal use this terminal should be tied to VDD 30 Cable I O Twisted pair cable A differentia...

Page 65: ...8 13 PIN CONFIGURATION 22 23 C_6 GPIO RED C_7 GPIO GREEN C_8 GPIO BLUE C_9 GPIO FSO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18...

Page 66: ...ernal single ended oscillator Digital Video C 9 0 GPIO 9 0 57 58 59 60 63 64 65 66 69 70 O Digital video output of CbCr C 9 is MSB and C 0 is LSB Unused outputs can be left unconnected Also these terminals can be programmable general purpose I O For the 8 bit mode the two LSBs are ignored D_BLUE 58 I Digital BLUE input from overlay device D_GREEN 59 I Digital GREEN input from overlay device D_RED ...

Page 67: ...3_A33VDD CH4_A33VDD 4 5 20 21 I Analog power Connect to 3 3 V DGND 27 32 42 56 68 I Digital return DVDD 31 41 55 67 I Digital power Connect to 1 8 V IOGND 39 49 62 I Digital power return IOVDD 38 48 61 I Digital power Connect to 3 3 V or less for reduced noise PLL_A18GND 77 I Analog power return PLL_A18VDD 76 I Analog power Connect to 1 8 V Sync Signals HS CS GPIO 72 I O Horizontal sync output or ...

Page 68: ...041 Power Distribution Switches BLOCK DIAGRAM OUT OC IN EN GND Current Limit Driver UVLO Charge Pump CS Thermal Sense Power Switch Current Sense Figure 8 15 PIN CONFIGURATION 1 2 3 4 8 7 6 5 GND IN IN EN OUT OUT OUT OC TPS2041 D OR P PACKAGE TOP VIEW Figure 8 16 ...

Page 69: ... active low OUT 6 7 8 6 7 8 O Power switch output IC7521 L5972D 2A Switch Step Down Switching Regulator PIN DESCRIPTION AND CONFIGURATION PIN CONNECTION PIN DESCRIPTION N Pin Function 1 OUT Regulator Output 2 3 6 7 GND Ground 4 COMP E A output for frequency compensation 5 FB Feedback input Connecting directly to this pin results in an output voltage of 1 23V An external resistive divider is requir...

Page 70: ...mmable Delay BLOCK DIAGRAM NCP303LSNxxT1 Open Drain Output Configuration Vref 2 Input 3 Gnd 5 CD RD 1 Reset Output Figure 8 17 PIN DESCRIPTION AND CONFIGURATION PIN CONNECTIONS AND MARKING DIAGRAM 1 3 N C Reset Output 2 Input Ground 4 CD 5 xxxYW Top View xxx 302 or 303 Y Year W Work Week Figure 8 18 ...

Page 71: ...EN 71 3139 785 3093x P003 P001 P002 3139 249 2798 2005 03 02 Exploded View of the Set Figure 9 1 9 Exploded View Spare Parts List ...

Page 72: ...62411 COVER TRAY ASSY DVDR3305 0920 3143 027 62251 FRAME ASSY 1001 3139 248 86731 DIGITAL BOARD DVDR3365 05 only 1001 3139 248 84651 DIGITAL BOARD DVDR3365 02 19 only 1001 3139 248 86721 DIGITAL BOARD DVDR3365 51 only 1001 3139 248 86691 DIGITAL BOARD DVDR3305 05 only 1001 3139 248 86061 DIGITAL BOARD DVDR3305 02 19 only 1001 3139 248 86681 DIGITAL BOARD DVDR3305 51 only 1001 3139 248 86711 DIGITA...

Page 73: ...EN 73 3139 785 3093x 10 REVISION LIST Version 1 0 Original Release Version 1 1 Add missing Exploded View drawing 10 Revision List ...

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