TDA7703/TDA7703R
7.0 Overall system performance
7.1 FM overall system performance
Antenna level equivalence: 0dB
μ
V = 1
μ
V
rms
(Antenna terminal voltage with 50
Ω
source); no antenna dummy
Reference deviation = 40 kHz, de-emphasis = 50 us, f
audio
= 1 KHz, V
rf
= 60 dBu
Unless otherwise specified.
Limits
Symbol
Parameter
Test Condition, Comments
Min Typ Max
Units
Tuning range FM Eu
(can be modified by the user)
87.5
108
MHz
Tuning step FM Eu
(can be modified by the user)
100
kHz
Tuning range FM US
(can be modified by the user)
87.5
107.9
MHz
Tuning step FM US
(can be modified by the user)
200
kHz
Tuning range FM Jp
(can be modified by the user)
76
90
MHz
Tuning step FM Jp
(can be modified by the user)
100
kHz
Tuning range FM EEu
(can be modified by the user)
65
74
MHz
Tuning step FM EEu
(can be modified by the user)
100
kHz
Sensitivity
S/N
=26dB
-4
dBu
S/N
@ 10dBu, no highcut, DISS
BW = #2
TBD dB
@ 60dBu, mono
75
dB
@ 60dBu, Deviation = 75
kHz, mono
81 dB
Ultimate
S/N
@ 60dBu, stereo
73
dB
Distortion
Deviation=
75
kHz
0.05
%
Max
deviation
THD=3%
TBD
kHz
Adjacent channel Selectivity
Δ
F=100kHz, SINAD=30dB
desired 40 dBu, dev=40kHz,
400Hz
undesired. dev=40kHz, 1Khz
TBD dB
Alternate Channel Selectivity
Δ
F=200kHz, SINAD=30dB
desired 40 dBu, dev=40kHz,
400Hz
undesired. dev=40kHz, 1kHz
TBD dB
Max. Strong Signal Interferer
Desired = 10dBu
SINAD = 30dB
Undesired
Δ
F = 1MHz
TBD dBu
Desired = 40dBu,
dev=40kHz, 400Hz,
SINAD=30dB
Undesired1 =±400kHz,
dev=40kHz, 1 kHz
Undesired2=±800kHz, no
mod
TBD dBu
3 signal performance
Desired = 40dBu,
dev=40kHz, 400Hz,
SINAD=30dB
Undesired1 =±1MHz,
dev=40kHz, 1 kHz
Undesired2=±2MHz, no mod
TBD dBu
AM
suppression m=30%
70
dB
Image
rejection
70
dB
Logarithmic field strength
indicator
@40 dBu
read “FM_Smeter_log”
-0.33
(equiv.
to 37
dBu)
-0.3
-0.27
(equiv.
to 43
dBu)
-
Rev. 1.0
12/22
Summary of Contents for CEM5000/00
Page 7: ...SET BLOCK DIAGRAM 3 1 3 1 ...
Page 8: ...SET WIRING DIAGRAM 4 1 4 1 ...
Page 9: ...5 1 5 1 CIRCUIT DIAGRAM MAIN BOARD PART 1 ...
Page 10: ...5 2 5 2 CIRCUIT DIAGRAM MAIN BOARD PART 2 ...
Page 11: ...CIRCUIT DIAGRAM MAIN BOARD PART 3 5 3 5 3 ...
Page 12: ...CIRCUIT DIAGRAM MAIN BOARD PART 4 5 4 5 4 ...
Page 13: ...CIRCUIT DIAGRAM MAIN BOARD PART 5 5 5 5 5 ...
Page 14: ...5 6 LAYOUT DIAGARM MAIN BOARD TOP SIDE VIEW 5 6 ...
Page 15: ...LAYOUT DIAGARM MAIN BOARD BOTTOM SIDE VIEW 5 7 5 7 ...
Page 17: ...LAYOUT DIAGRAM PANEL BOARD 6 2 6 2 ...
Page 18: ...CIRCUIT DIAGRAM SERVO BOARD PART 1 7 1 7 1 ...
Page 19: ...CIRCUIT DIAGRAM SERVO BOARD PART 2 7 2 7 2 ...
Page 20: ...LAYOUT DIAGRAM SERVO BOARD TOP SIDE VIEW 7 3 7 3 ...
Page 21: ...LAYOUT DIAGRAM SERVO BOARD BOTTOM SIDE VIEW 7 4 7 4 ...
Page 31: ......
Page 82: ...TDA7703 TDA7703R 11 PACKAGE INFORMATION Rev 1 0 21 22 ...