TDA7703/TDA7703R
6.12.1 I
2
C interface
The following parameters apply to the serial bus communication when I
2
C protocol has been selected at
start-up. For the other electrical characteristics of the pins, section 6.9 applies. The parameters of the
following table are defined as in Figure 1.
Limits
Symbol
Parameter
Test Condition, Comments
Min Typ Max
Units
f
SCL
SCL Clock frequency
100
500
kHz
t
AA
SCL low to SDA data valid
300
ns
t
buf
time the bus must be kept
free before a new
transmisison
4.7
us
t
HD-STA
START condition hold time
4.0
us
t
LOW
Clock
low
period
4.7
us
t
HIGH
Clock high period
4.0
us
t
SU-SDA
START condition setup time
4.7
us
t
HD-DAT
Data input hold time
0
us
t
SU-DAT
Data input setup time
250
ns
t
R
SDA & SCL rise time
1000
ns
t
F
SDA & SCL full time
300
ns
t
SU-STOP
Stop condition setup time
4.0
us
t
DH
Data out time
300
ns
Figure 1
I
2
C bus timing diagram
Rev. 1.0
11/22
Summary of Contents for CEM5000/00
Page 7: ...SET BLOCK DIAGRAM 3 1 3 1 ...
Page 8: ...SET WIRING DIAGRAM 4 1 4 1 ...
Page 9: ...5 1 5 1 CIRCUIT DIAGRAM MAIN BOARD PART 1 ...
Page 10: ...5 2 5 2 CIRCUIT DIAGRAM MAIN BOARD PART 2 ...
Page 11: ...CIRCUIT DIAGRAM MAIN BOARD PART 3 5 3 5 3 ...
Page 12: ...CIRCUIT DIAGRAM MAIN BOARD PART 4 5 4 5 4 ...
Page 13: ...CIRCUIT DIAGRAM MAIN BOARD PART 5 5 5 5 5 ...
Page 14: ...5 6 LAYOUT DIAGARM MAIN BOARD TOP SIDE VIEW 5 6 ...
Page 15: ...LAYOUT DIAGARM MAIN BOARD BOTTOM SIDE VIEW 5 7 5 7 ...
Page 17: ...LAYOUT DIAGRAM PANEL BOARD 6 2 6 2 ...
Page 18: ...CIRCUIT DIAGRAM SERVO BOARD PART 1 7 1 7 1 ...
Page 19: ...CIRCUIT DIAGRAM SERVO BOARD PART 2 7 2 7 2 ...
Page 20: ...LAYOUT DIAGRAM SERVO BOARD TOP SIDE VIEW 7 3 7 3 ...
Page 21: ...LAYOUT DIAGRAM SERVO BOARD BOTTOM SIDE VIEW 7 4 7 4 ...
Page 31: ......
Page 82: ...TDA7703 TDA7703R 11 PACKAGE INFORMATION Rev 1 0 21 22 ...