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FEDD56V16160F-02

Semiconductor

MSM56V16160F

13/31

Page Read & Write Cycle (Same Bank) @

CAS

Latency

====

2, Burst Length=4

*Note: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the

write command to avoid bus contention.

2. To assert row precharge before a burst write ends, wait t

after the last write data input.

Input data during the precharge input cycle will be masked internally.

CLK

CKE

RAS

CAS

ADDR

A11

A10

UDQM,
LDQM

Read Command

Write Command

Precharge Command

Qa0 Qa1 Qb0 Qb1

Dc0 Dc1

Dd0

Cc0

Cd0

Ca0

Cb0

CCD

∗

Note 2

∗

Note 1

Bank A Active

OWD

High

Summary of Contents for CEM3000B

Page 1: ...TROUBLE SHOOTING 21 22 2011 11 17 CEM3000B ÌËÒÛÎ ò Ý ÎÝË Ì Ü ßÙßÓ ÌËÒÛÎ ÞÑßÎÜ òòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòòç ïðóïï ïîóïí ïìóïë ïêóïé è ïç îð ...

Page 2: ...plift the CD deck mechanism and take out FFC then take out deck mechanism The procedure of disassemblin钮 the panel 1 Press EJ button and take out panel take out A screw in top cover of the unit Use tweezer to prize up top cover as the blue arrow direction which showed as below picture 2 Use electrical screw bit to take out B C two screws in left and right side of metal bracket Then take out D E sc...

Page 3: ...3 ...

Page 4: ...É Î ÒÙ Ü ßÙÎßÓ ì ...

Page 5: ...137 NC GND OUTSW OUTRL2 OUTRF OUTRR OUTLF MUTE SCL SDA VDD SAIN SAOUT VREF MIX SW OUTRR2 OUTLR DIFR SE0R CREF DIFFG DIFFL SE0L SE1L SE1R SE2R SE2L SE3R ACINR SE3L ACINL ACOUTL AC2OUT ACINL FILOL ACINR FILOR AC AC2OUTR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 U5 TDA7419 SUB_OUT BEEP VCC 1 2 3 4 5 6 CON10 AV 4P C32 NC AUX_R AUX_L MUTE MUTE1 C5V USB_5V EC15 100UF R22...

Page 6: ...CIRCUIT DIAGAM SERVO BOARD ê ...

Page 7: ... CLK DATA INH GND GND B G R DO LCK D2 D1 TRACK UP TRACK DN USB_5V USB_DN USB_UP AUX_R AUX_L GND DO CLK CE CE GND M1 SC6579 M2 M3 SUB DBB EQ ipod VOL VOL EJ BAND AUDIO MENU DISP POWER MUTE R956 R957 Q903 Q901 Q902 R955 3K3 4K7 R913 8K2 M4 M5 M6 é Ý ÎÝË Ì Ü ßÙÎßÓ ÐßÒÛÔ ÞÑßÎÜ ...

Page 8: ...è CIRCUIT DIAGAM REMOTE BOARD ...

Page 9: ...SI SCL RDSINT RSTN SCL SDA_MOSI VDIG RSTN RDSINT VDIG DACOUT_R DACOUT_L VRF FMANT VIF VRF VIF VDIG AMANT GND RF GND RF 470nF 10nF 1uH LQM21PN1R0MC00 MuRata 100nF 100nF 1uF 1UF 1UF 100nF 68pF 10nF 100nF 220 1 LF1 2 TCAGCFM 3 FMMIXDEC 4 FMMIXIN 32 GND 1V2 33 VCC DAC 5 GND RF 6 FMPINDRV 7 VCC RF 8 TCAM 9 PINDDEC 10 PINDIN 11 GND LNA 23 VCCREG12 24 REG 1V2 25 VDD 3V3 31 VDD 1V2 30 RSTN 29 RDSINT 28 VD...

Page 10: ...10 Óß Ò ÐÝÞ ÝÑÓÐÑÒÛÒÌ ÔßÇÑËÌ ÞÑÌÌÑÓ Í ÜÛ Ê ÛÉ ...

Page 11: ...Óß Ò ÐÝÞ ÝÑÓÐÑÒÛÒÌ ÔßÇÑËÌ ÌÑÐ Í ÜÛ Ê ÛÉ 11 ...

Page 12: ...12 SERVO PCB COMPONENT LAYOUT TOP SIDE VIEW ...

Page 13: ...SERVO PCB COMPONENT LAYOUT BOTTOM SIDE VIEW 13 ...

Page 14: ...PANEL PCB COMPONENT LAYOUT BOTTOM SIDE VIEW 14 ...

Page 15: ...PANEL PCB COMPONENT LAYOUT TOP SIDE VIEW 15 ...

Page 16: ...REMOTEL PCB COMPONENT LAYOUT BOTTOM SIDE VIEW 16 ...

Page 17: ...REMOTEL PCB COMPONENT LAYOUT TOP SIDE VIEW 17 ...

Page 18: ...TUNER PCB COMPONENT LAYOUT BOTTOM SIDE VIEW 18 ...

Page 19: ...19 ÍÑ ÐÝÞ ÝÑÓÐÑÒÛÒÌ ÔßÇÑËÌ ...

Page 20: ...SET EXPLODER VIEW DRAWING 20 ...

Page 21: ...or U5 TDA7419 should be 9V0 g To check the resistor network of NR1 4K7 H To check the voltage of the15 pin Lamp Vcc of CN5 should be 6V4 2 NO audio output a To check whether the volume knob is turn to the minimum position b To check whether the unit is at MUTE mode press SOURCE button and check whether it is effective of the input sound source c To check whether the connection of 8 PIN audio outpu...

Page 22: ...mination and bad contact on the male female connector of the panel and main board If necessary can exchange the panel to test whether the defective is occurred by the unit or panel h To check the rotation mechanism of CD deck mechanism i To check whether the rotation belt of deck mechanism is dislocation or loose f To check the servo board connector of CN20P1 and main board connector of CN9 whethe...

Page 23: ... pin 22 Built in Standby switch function pin 4 Built in Self diagnosis function pin 25 Signal output in case of output offset detection shorting to VCC shorting to ground and load shorting Electric mirror noise decrease Built in various protection circuit shorting to ground shorting to VCC load shorting over voltage and thermal shut down No external anti oscillation part necessary Note1 Please do ...

Page 24: ...rical Characteristics at Ta 25 Vcc 14 4V RL 4Ω f 1kHz Rg 600Ω Parameter Symbol Conditions min typ max Unit Quiescent current Icco RL Rg 0Ω 200 400 mA Standby current Ist Vst 0V 10 uA Voltage gain VG Vo 0dBm 25 26 27 dB Voltage gain difference VG 1 1 dB Output power Po THD 10 23 28 W Pomax1 JEITA max 43 W Pomax2 Vcc 15 2 JEITA max 48 W Output offset voltage Vn offset Rg 0Ω 100 100 mV Total harmonic...

Page 25: ...ircuit The components and constant values within the test circuit are used for confirmation of characteristics and are not guarantees that incorrect or trouble will not occur in application equipment te circ it i le ilter rotective circ it D D D D D te cc cc Lo Level te D cc rotective circ it D tan itch D L L L L a ...

Page 26: ...d potential enabling audio muting The muting function is turned on by the applied voltage of 1V or less to the resistance of 10kΩ And the muting function is turn off when this pin opens Also the time constant of the muting function is determined by external capacitor and resistor constants It is concerned with a pop noise in amplifier ON OFF and mute ON OFF After enough examination please set it 3...

Page 27: ...e varies 6 Pop noise For pop noise prevention it is recommended to use the muting function at the same time Please turn on the muting function simultaneously with power supply on when the amplifier is turned on Next turn off the muting function after the output DC potential stabilization When the amplifier is turn off turn off the power supply after turning on the muting function Oscillation Stabi...

Page 28: ... THD 10 all channel is similar THD Po f 1kHz 0 01 0 1 1 10 0 1 1 10 100 Po W THD ch1 ch2 ch3 ch4 Vcc 14 4V RL 4Ω f 1kHz THD f 0 01 0 1 1 10 10 100 1000 10000 100000 f Hz THD ch1 ch2 ch3 ch4 Vcc 14 4V RL 4Ω Po 4W THD Po f 100Hz 0 01 0 1 1 10 0 1 1 10 100 Po W THD ch1 ch2 ch3 ch4 Vcc 14 4V RL 4Ω f 100Hz THD Po f 10kHz 0 01 0 1 1 10 0 1 1 10 100 Po W THD ch1 ch2 ch3 ch4 Vcc 14 4V RL 4Ω f 10kHz Po f T...

Page 29: ...R 0 20 40 60 80 10 100 1000 10000 100000 fR Hz SVRR dB ch1 ch2 ch3 ch4 Vcc 14 4V VccR 0dBm Rg 0Ω RL 4Ω CVcc 0 1μF CH Sep f CH1 0 20 40 60 80 10 100 1000 10000 100000 f Hz CH sep dB ch1 ch2 ch1 ch3 ch1 ch4 Vcc 14 4V RL 4Ω Rg 10kΩ Vo 0dBm CH Sep f CH2 0 20 40 60 80 10 100 1000 10000 100000 f Hz CH sep dB ch2 ch1 ch2 ch3 ch2 ch4 Vcc 14 4V RL 4Ω Rg 10kΩ Vo 0dBm CH Sep f CH3 0 20 40 60 80 10 100 1000 1...

Page 30: ...W Vcc 14 4V Vcc 16V f 1kHz RL 4Ω Pd Vcc Icc Po 4ch Offset DIAG Vcc 0 1 2 3 4 8 10 12 14 16 18 Vcc V Vosdet V RL 4Ω R 0Ω Detection Level Mute ATT V Mute 0 20 40 60 80 100 0 0 1 0 2 0 3 0 4 0 5 0 V Mute V Mute ATT dB Vcc 14 4V RL 4Ω Vo 20dBm Icco Vst 0 50 100 150 200 250 0 0 1 0 2 0 3 0 4 0 5 0 Vst V Icco mA Vcc 14 4V RL Open R 0Ω ...

Page 31: ......

Page 32: ... polysilicon CMOS 1 transistor memory cell 2 Bank 524 288 word 16 bit configuration Single 3 3V power supply 0 3V tolerance Input LVTTL compatible Output LVTTL compatible Refresh 4096 cycles 64ms Programmable data transfer mode CAS Latency 1 2 3 Burst Length 1 2 4 8 Full Page Data scramble sequential interleave CBR auto refresh Self refresh capability Packages 50 pin 400mil plastic TSOP Type II TS...

Page 33: ...Column Address Strobe NC No Connection WE Write Enable Note The same power supply voltage must be provided to every VCC pin and VCCQ pin The same GND voltage level must be provided to every VSS pin and VSSQ pin 50 Pin Plastic TSOP II K Type 24 19 20 21 22 23 14 15 16 17 18 7 44 37 36 35 34 33 32 31 30 29 28 27 A11 A10 VSSQ VCCQ VCCQ VSS NC UDQM NC A8 A7 A6 WE CAS RAS CS A0 A1 A2 LDQM A5 A4 CLK CKE...

Page 34: ...s Row column multiplexed Row address RA0 RA10 Column Address CA0 CA7 A11 Slects bank to be activated during row address latch time and selects bank for precharge and read write during column address latch time A11 L Bank A A11 H Bank B RAS CAS WE Functionality depends on the combination For details see the function truth table UDQM LDQM Masks the read data of two clocks later when UDQM and LDQM ar...

Page 35: ...ncy Burst Controller Internal Col Address Counter I O Controller Column Address Buffers Internal Row Address Counter Row Address Buffers 8 Row Decoder s Row Decoder s 12 Word Drivers Word Drivers 8Mb Memory Cells 8Mb Memory Cells Read Data Registe r Output Buffers Column Decoders Sense Amplifiers Input Data Registe r Input Buffers CKE CLK CS WE UDQM LDQM A11 8 12 16 16 16 16 16 8 ...

Page 36: ...W Short Circuit Output Current IOS 50 mA Operating Temperature Topr Ta 25 C RECOMMENDED OPERATIING CONDITIONS Voltages referenced to VSS 0V Parameter Symbol Min Typ Max Unit Power Supply Voltage VCC VCCQ 3 0 3 3 3 6 V Input High Voltage VIH 2 0 VCC 0 2 V Input Low Voltage VIL 0 3 0 8 V PIN CAPACITANCE VBIAS 1 4V Ta 25 C f 1 MHz Parameter Symbol Min Max Unit Input Capacitance CLK CCLK 2 5 4 pF Inpu...

Page 37: ...echarge CKE VIH tCC Min 35 30 mA 3 Average Power Supply Current Clock Suspension ICC3S Both Banks Active CKE VIL tCC Min 3 3 mA 2 Average Power Supply Current Active Standby ICC3 One Bank Active CKE VIH tCC Min 40 35 mA 3 Power Supply Current Burst ICC4 Both Banks Active CKE VIH tCC Min 125 100 mA 1 2 Power Supply Current Auto Refresh ICC5 One Bank Active CKE VIH tCC Min tRC Min 80 70 mA 2 Average...

Page 38: ...ds of Power on Sequence POWER ON SEQUENCE 1 1 With inputs in NOP state turn on the power supply and start the system clock 2 After the VCC voltage has reached the specified level pause for 200µs or more with the input kept in NOP state 3 Issue the precharge all bank command 4 Apply a CBR auto refresh eight or more times 5 Enter the mode register setting command POWER ON SEQUENCE 2 1 With inputs in...

Page 39: ...rom Clock tOLZ 3 3 ns Output High Impedance Time from Clock tOHZ 8 8 ns Output Hold from Clock tOH 3 3 ns 3 Random Read or Write Cycle Time tRC 70 90 ns RAS Precharge Time tRP 20 30 ns RAS Pulse Width tRAS 48 100 000 60 100 000 ns RAS to CAS Delay Time tRCD 20 30 ns Write Recovery Time tWR 8 15 ns RAS to RAS Bank Active Delay Time tRRD 20 20 ns Refresh Time tREF 64 64 ms Power down Exit setup Time...

Page 40: ...charge Command lROH CL CL Cycle Active Command Input Time from Mode Register Set Command Input Min lMRD 2 2 Cycle Write Command Input Time from Output lOWD 2 2 Cycle Notes 1 AC measurements assume that tT 1ns 2 The reference level for timing of input signals is 1 4V 3 Output load 4 The access time is defined at 1 4V 5 If tT is longer than 1ns then the reference level for timing of input signals is...

Page 41: ...S CAS CAS Latency 2 Burst Length 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM tOH Ra Ca0 tRP tRC Qa1 Cb0 Rb Rb Ra Qa0 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOHZ tWR Row Active Read Command Precharge Command Row Active Write Command Precharge Command tRCD ...

Page 42: ... 2 Burst Length 4 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Row Active 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High tOLZ Db tSI Qc tHI Qa tOH Ra lOWD BS BS BS BS BS Ra Cc Cb Ca tOHZ tAC tHI tSI tSI tHI tHI tSI tSI tHI tHI tSI ICCD tSI tCL tCC tCH Read Command Write Command Read Command Precharge Command ...

Page 43: ...ration 0 0 After the end of burst bank A holds the idle status 1 0 After the end of burst bank A is precharged automatically 0 1 After the end of burst bank B holds the idle status 1 1 After the end of burst bank B is precharged automatically 4 When issuing a precharge command the bank to be precharged is selected by the A10 and A11 inputs A10 A11 Operation 0 0 Bank A is precharged 0 1 Bank B is p...

Page 44: ...o avoid bus contention 2 To assert row precharge before a burst write ends wait tWR after the last write data input Input data during the precharge input cycle will be masked internally 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Read Command Read Command Write Command Write Command Precharge Command Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Cc0 Cd0 Ca0 Cb0 ...

Page 45: ...LDQM A Bank Precharge Start Row Active B Bank A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point A Bank Precharge Start A Bank Precharge Start High Ra tRRD Qa0 tWR Rb Ra Rb Ca Cb Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 CAS Latency 2 CAS Latency 3 CAS Latency 1 Row Active A Bank DQ DQ UDQM LDQM UDQM LDQM ...

Page 46: ...11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 Row Active A Bank Read Command A Bank Precharge Command A Bank Row Active B Bank Read Command B Bank Precharge Command B Bank Row Active A Bank Read Command A Bank tRRD tRC High ...

Page 47: ...10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb RAc CAc RAa RBb RAc DAa0 DAa1 DAa2 DAa3 Row Active A Bank Write Command A Bank Precharge Command A Bank Row Active B Bank Write Command B Bank Precharge Command B Bank Row Active A Bank Write Command A Bank DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 High Precharge Command A Bank ...

Page 48: ... CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb CAc CBd CAe RAa RBb QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Note 1 Row Active A Bank Read Command A Bank Row Active B Bank Read Command B Bank Precharge Command A Bank Read Command A Bank Read Command A Bank Read Command B Bank IROH High ...

Page 49: ... 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Row Active A Bank Row Active B Bank Write Command A Bank Precharge Command Both Bank High RAa CAa RAa RBb RBb CBd DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 Write Command B Bank Write Command A Bank Write Command B Bank DAa2 DAa1 DAa0 CAc CBb ...

Page 50: ...CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 Row Active A Bank Read Command A Bank Precharge Command A Bank Row Active B Bank Write Command B Bank Row Active A Bank Read Command A Bank High ...

Page 51: ...Cycle CAS CAS CAS CAS Latency 2 Burst Length 4 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CAa0 CBb0 CAc0 QAa0 QAa1 QAa2 QAa3 Read Command A Bank Write Command B Bank Read Command A Bank DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 High QAc2 QAc3 ...

Page 52: ...DQM are asserted the write data in the same clock cycle is masked 4 When LDQM is set High the input output data of DQ1 DQ8 is masked 5 When UDQM is set High the input output data of DQ9 DQ16 is masked CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ra Ca Cb Cc Ra Qa0 Qa1 Qa2 Qb0 Qb1 Dc0 Note 1 Row Active Read Command CLOCK Suspension Read DQM CLOCK...

Page 53: ...EAD can be interrupted by WRITE The minimum command interval is burst length 1 cycles UDQM LDQM must be high at least 3 clocks prior to the write command CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ra Ca0 Cb0 Ra Db0 Db1 Note 1 Row Active Read Command Write Command Precharge Command tWR tRCD Db2 Db3 Da0 ...

Page 54: ... data will not output after lROH equals CAS latency 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM CAS Latency 2 CAS Latency 3 Ra Ca Note 1 Qa0 Qa1 Ra Qa2 Note 1 Qa3 Qa4 Qa5 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Row Active Read Command Precharge Command lROH lROH Qa5 lROH High CAS Latency 1 DQ DQ UDQM LDQM UDQM LDQM ...

Page 55: ... UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CAS Latency 2 CAS Latency 3 Qa0 Qa1 Qa2 Qa3 Qa4 Qa0 Qa1 Qa2 Qa3 Qa4 Qa0 Qa1 Qa2 Qa3 Qa4 CAS Latency 1 Read Command Cb Qb0 Qb1 Qb2 Qb3 Qb4 Qb0 Qb1 Qb2 Qb3 Qb4 Qb0 Qb1 Qb2 Qb3 Qb4 Burst Stop Command Write Command Burst Stop Command High Ca DQ DQ UDQM LDQM UDQM LDQM ...

Page 56: ... maintains the mode while CKE is low 2 To release the circuit from power down mode CKE has to be set high for longer than tPDE tSI 1CLK CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ra Ca Ra Qa0 Qa1 Qa2 Note 2 Power down Entry Row Active Power down Exit Precharge Command Read Command Clock Suspension Exit tSI Note 1 Clock Suspension Entry tPDE tS...

Page 57: ...FEDD56V16160F 02 1 Semiconductor MSM56V16160F 26 31 Self Refresh Cycle 0 1 2 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Ra BS Ra Self Refresh Entry Self Refresh Exit Row Active tSI tRC Hi Z ...

Page 58: ...nductor MSM56V16160F 27 31 Mode Register Set Cycle Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 CLK CKE CS RAS CAS ADDR DQ WE UDQM LDQM New Command lMRD Auto Refresh tRC MRS Auto Refresh Key Ra Hi Z Hi Z High High 0 1 2 3 4 5 6 ...

Page 59: ...new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst execute Row Precharge Read L L L X X X ILLEGAL H X X X X X NOP Continue Row Active after Burst ends L H H H X X NOP Continue Row Active after Burst ends L H H L X X Term Burst Row Active L H L H BA CA A10 Term Burst start new Burst Read 3 L H L L BA CA A10 Term Burst start new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 T...

Page 60: ...H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 Row Active L L L X X X ILLEGAL H X X X X X NOP Idle after tRC L H H X X X NOP Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL Refresh L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL Mode Register Access L L X X X X ILLEGAL ABBREVIATIONS RA Row Address BA Ba...

Page 61: ...Continue power down mode H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL All Banks Idle 7 ABI L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Ne...

Page 62: ...a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercia...

Page 63: ...Confidential S5L8035Ui Preliminary Spec PRODUCT OVERVIEW 1 1 S5L8035Ui CDMP3 SOC V1 1 ...

Page 64: ...ssor SDRAM Serial Flash 4 channel timers I O ports audio PWM processor 1 channel UARTs with handshake IIC BUS interface IIS interface SPI interface PLLs for clock generation Especially one newly adopted feature of S5L8035Ui micro architecture make the solution more cost effective CalmADM a cost effective MCU DSP solution based on Samsung s 16 bit MCU CalmRISC16 and Samsung s 24 bit audio DSP CalmM...

Page 65: ...l S Flash Internal ROM Internal SRAM External SDRAM EDO Core peripherals IIC UART SPI IR I O etc AUDIO Stream Codec MPEG 1 2 2 5 decoding WMA decoding Output channel 2 channel Audio PWM output Sample rate 8kHz 48 kHz SYSTEM Data input FEU CD 4x Peripheral interface UART SPI IR RTC I2C Timer GPIO Memory 32KB Internal SRAM 3 5Mbits Internal ROM Serial Flash SDRAM EDO PHYSICAL Operating voltage 3 3V ...

Page 66: ...eration in 1 cycle 2 multiplier accumulator registers 4 general accumulator registers and 8 pointer registers I Cache Memory A direct mapped I Cache 4KB 16 entries 8 words with one valid bit per line D Cache Memory 2 way set associative data caches X and Y Caches 6KB each 8 entries 6 words with one valid bit and one dirty bit per a Mac data line 8 entries 4 words with one valid bit and one dirty b...

Page 67: ...down mode S W Reset by MCU for Peripheral module reset Interrupt Controller 32 interrupt sources Watch dog timer 4 Timers UART 4 External interrupts IIC IIS SPI IR Edge detect mode on external interrupt source Programmable polarity of rising and falling Supports FIQ Fast Interrupt request for very urgent interrupt request Timers 16 bit timer 1 2 Interval free run one shot and capture mode Programm...

Page 68: ...Generator Checker Normal and DMA data Transfer Mode Support for Block and Multi block data Read and Write MSTICK Interface Support Memory Stick Serial Peripheral Interface SPI SPI protocol compatible Polling Interrupt DMA transfer mode Max 20Mbps burst transmit receive rate used by IODMA RTC Supports Real Time Clock Watchdog Timer 11 bit Watchdog Timer Interrupt request or system reset at time out...

Page 69: ...Confidential S5L8035Ui PRELIMINARY SPEC PRODUCT OVERVIEW 1 7 Figure 1 2 S5L8035Ui 128 Pin Assignments ...

Page 70: ...temperature 65 to 150 o C RECOMMENDED OPERATING CONDITIONS Table 29 2 Recommended Operating Conditions Symbol Parameters Condition Min Type Max Unit VDD 1 2V core DC supply voltage Commercial industrial 1 1 1 2 1 3 V VDDP 3 3V I O DC supply voltage Commercial Industrial 3 0 3 3 3 6 V VIN DC input voltage 3 3V input buffer 3 0 3 3 3 6 V VOUT DC output voltage 3 3V output buffer 3 0 3 3 3 6 V TOPR O...

Page 71: ...V Hysteresis Voltage 0 1VDD V High Level Input Current Input Buffer Vin VDD 10 10 uA VDD 3 3V 20 70 130 VDD 2 5V 10 40 80 IIH Input Buffer with pull down Vin VDD VDD 1 8V 5 20 40 uA Low Level Input Current Input Buffer Vin VSS 10 10 uA VDD 3 3V 130 70 20 VDD 2 5V 80 40 10 IIL Input Buffer with pull up Vin VSS VDD 1 8V 40 20 5 uA VOH IOH 100uA VDD 0 2 V VOH IOL 100uA 0 2 V IOZ Tri State Output Leak...

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