92
BJ2.4U/BJ2.5U LA
7.
Circuit Diagrams and PWB Layouts
SSB: PNX2015: DV I/O Interface
DV5_DATA_3
DV5_DATA_4
DV5_DATA_5
DV5_DATA_6
DV5_DATA_7
DV5_DATA_8
DV5_DATA_9
DV1_DATA6
DV1_DATA7
DV1_DATA8
DV1_DATA9
DV1_VALID
DV2_CLK
DV2_DATA0
DV2_DATA1
DV2_DATA2
DV2_DATA3
DV2_DATA4
DV2_DATA5
DV2_DATA6
DV2_DATA7
DV2_DATA8
DV2_DATA9
DV2_VALID
DV3_CLK
DV3_DATA0
DV3_DATA1
DV3_DATA2
DV3_DATA3
DV3_DATA4
DV3_DATA5
DV3_DATA6
DV3_DATA7
DV3_DATA8
DV3_DATA9
DV3_VALID
DV4_DATA_0
DV5_DATA_1
DV5_DATA_2
DV4_DATA_1
DV4_DATA_2
DV4_DATA_3
DV4_DATA_4
DV4_DATA_5
DV4_DATA_6
DV4_DATA_7
DV4_DATA_8
DV4_DATA_9
DV5_DATA_0
DV_CLK
DV_FREF
DV_HREF
DV_VALID
DV_VREF
DV1_CLK
DV1_DATA0
DV1_DATA1
DV1_DATA2
DV1_DATA3
DV1_DATA4
DV1_DATA5
GIN4
GIN5
GIN6
GIN7
GIN8
RIN9
LVDS_AN
LVDS_AP
LVDS_BN
LVDS_BP
LVDS_CLKN
LVDS_CLKP
LVDS_CN
LVDS_DP
LVDS_EN
LVDS_EP
BIN3
RGB_CLK_IN
RGB_UD
RGB_HSYNC
RGB_DE
GIN3
RGB_VSYNC
GIN9
BIN0
BIN1
BIN2
BIN4
BIN5
BIN6
BIN7
BIN8
BIN9
GIN0
RIN0
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
RIN7
RIN8
LVDS_CP
LVDS_DN
GIN1
GIN2
3LR4-3 B4
3LR4-4 B4
3LR5-2 C4
3LR5-3 B4
3LR5-4 B4
3LR6-1 C4
6
7
8
9
A
2
3
4
5
6
7
B
C
D
E
A
B
C
D
E
2LT7 D8
3LR0 D4
3LR1 C4
3LR3-1 B4
3LR3-2 B4
3LR3-3 B4
3LR3-4 B4
3LR4-1 B4
3LR4-2 B4
1
2
2015
2015
PNX 2015: DV I/O Interface
1
3LR6-2 C4
3LR6-3 C4
3LR6-4 C4
8
9
3LR9-1 D4
3LR9-2 D4
3LR9-3 D4
3LR9-4 D4
3LS0-2 E4
3LS0-3 D4
3LS0-4 D4
3LS1-1 D4
3LS1-2 D4
3LS1-3 D4
3LS1-4 D4
7J00-2 B7
7J00-4 A2
AJ10 C8
3
4
5
3LR7-1 C4
3LR7-2 D4
3LR7-3 C4
3LR8-1 C4
3LR8-2 C4
3LR8-3 C4
3LR8-4 C4
22p
2LT7
33R
3LR7-1
AJ10
33R
3LR6-3
3LR3-3
33R
33R
3LR4-1
3LR1
33R
3LR4-4
33R
3LS1-3
33R
33R
3LR9-2
3LR8-4
33R
33R
3LS1-4
33R
3LS0-4
33R
3LR7-3
3LR6-4
33R
3LR8-2
33R
3LR3-2
33R
33R
3LR3-4
3LS1-1
33R
33R
3LR5-3
3LR5-2
33R
AJ3
AK2
AK8
AK9
AH9
AH8
AJ9
AH6
AG6
AF6
AK5
AH5
AG5
AK4
AJ4
AH4
AK3
AK29
AH28
AK30
AG8
AK7
AJ7
AH7
AG7
AF7
AK6
AJ6
AF27
AK28
AJ30
AH29
AG29
AG30
AH30
AG28
AH27
AJ28
AF30
AE30
AF28
AD27
AD26
AD30
AE26
AE27
AE28
AE29
AG27
AA30
AA29
AA28
AB29
AB28
AC30
AC28
AC27
AB30
AD29
7J00-4
PNX
DV INPUT
Φ
AD28
AB27
33R
3LS0-3
3LR8-1
33R
33R
3LR8-3
33R
3LR4-2
3LR7-2
3LR5-4
33R
33R
J28
A27
A28
A29
A30
B28
B30
C28
C29
C30
D27
D25
E25
B24
C24
E24
F24
J30
K26
J29
J27
F26
F27
F28
F29
B26
C26
A25
B25
C23
D23
G29
G30
H27
H28
H30
J26
D28
D29
D30
E27
E28
E30
F30
G26
G27
G28
OUTPUT INTERFACE
Φ
PNX
7J00-2
33R
3LR4-3
33R
3LR3-1
3LR9-3
33R
3LS1-2
33R
33R
3LR6-2
3LS0-2
33R
3LR9-4
33R
33R
3LR0
33R
3LR9-1
3LR6-1
33R
DV2A-CLK
DV3F-CLK
DV2A-VALID
DV2A-DATA1_ERR
DV2A-DATA3_1
DV2A-DATA5_3
DV2A-DATA6_4
DV2A-DATA8_6
DV3F-DATA0_SOP
DV3F-DATA3_1
DV3F-DATA5_3
DV3F-DATA6_4
DV3F-DATA8_6
DV1F-VALID
DV1F-DATA3
DV1F-DATA2
DV1F-DATA1
DV1F-DATA0
DV1F-DATA7
DV1F-DATA6
DV1F-DATA5
DV1F-DATA4
DV1F-DATA8_ERR
DV1F-DATA9_SOP
DV2A-DATA2_0
DV2A-DATA0_SOP
DV2A-DATA7_5
DV2A-DATA4_2
DV2A-DATA9_7
DV3F-VALID
DV3F-DATA2_0
DV3F-DATA1_ERR
DV3F-DATA7_5
DV3F-DATA4_2
DV3F-DATA9_7
MP-OUT-FFIELD
DV1F-CLK
DV4-DATA5_3
DV4-DATA6_4
DV4-DATA7_5
DV4-DATA8_6
DV4-DATA9_7
DV5-DATA0_SOP
DV5-DATA1_ERR
DV5-DATA2_0
DV5-DATA3_1
DV5-DATA4_2
DV5-DATA5_3
DV5-DATA6_4
DV5-DATA7_5
DV5-DATA8_6
DV5-DATA9_7
DV4-CLK
DV-FREF
DV-HREF
DV4-VALID
DV-VREF
TXPNXC-
TXPNXD-
TXPNXE-
MP-CLKOUT
MP-OUT-DE
MP-OUT-HS
MP-OUT-VS
MP-ROUT-0
MP-ROUT-1
MP-ROUT-2
MP-ROUT-3
MP-ROUT-4
MP-ROUT-5
MP-ROUT-6
MP-ROUT-7
MP-ROUT-8
MP-ROUT-9
DV4-DATA0_SOP
DV4-DATA1_ERR
DV4-DATA2_0
DV4-DATA3_1
DV4-DATA4_2
MP-BOUT-0
MP-BOUT-1
MP-BOUT-2
MP-BOUT-3
MP-BOUT-4
MP-BOUT-5
MP-BOUT-6
MP-BOUT-7
MP-BOUT-8
MP-BOUT-9
MP-GOUT-0
MP-GOUT-1
MP-GOUT-2
MP-GOUT-3
MP-GOUT-4
MP-GOUT-5
MP-GOUT-6
MP-GOUT-7
MP-GOUT-8
MP-GOUT-9
TXPNXA-
TXPNXB-
TXPNXCLK-
T
B4B
B4B
3104 313 6145.2
G_15930_032.eps
120606