10.
Circuit Diagrams and PWB Layouts
UART, IR-in/out
1
8
750_611_100927.ep
s
100927
UART, IR-in/o
u
t
P02J
P02J
2010-06-16
2
2010-02-05
1
8
204 000 90
8
0
AV-PIP BROADCOM
V+
V-
VCC
C1+
C1-
C2+
T2
T1
IN
IN
OUT
OUT
GND
T1
C2-
R2
R1
T2
R1
R2
V+
V-
VCC
C1+
C1-
C2+
T2
T1
IN
IN
OUT
OUT
GND
T1
C2-
R2
R1
T2
R1
R2
IR_OUT
DAA_AOUT
IR_IN0
UART2
3
FT1 E
3
3
FT2 E
3
7F10-1
3
F2
7FT0 A2
7FT1 C2
9FT0 B4
UART0
S
TRAPBIT
1FT
3
C6
1FT4 D6
1FT5 E6
2FT0 A2
2FT1 A
3
2FT2 B4
2FT
3
B2
2FT4 C2
2FT5 D
3
2FT6 D4
2FT7 D2
3
FT0 C
3
MAIN CON
S
OLE
UART1
9FT
3
D4
9FT4 E4
9FT5 E4
FF
S
2 C5
FF
S3
C6
FF
S
4 C5
5
6
1
2
3
4
5
6
A
B
C
D
E
F
9FT1 C4
9FT2 D4
A
B
C
D
E
F
1FT0 B1
1FT1 D1
1FT2 E1
UART1-
3
V
3
VIDEO DECODER
DEBUG
1
2
3
4
UART2-
3
V
3
UART0-
3
V
3
S
TRAPBIT
1
2
3
4
5
1FT0
BM0
3
B-
S
R
SS
-TBT
2FT5
100n
2FT4
100n
9FT5
9FT4
3
4
5
BM0
3
B-
S
R
SS
-TBT
1FT1
1
2
100n
2FT2
100n
2FT6
2
3
4
5
BM0
3
B-
S
R
SS
-TBT
1FT2
1
9FT1
1
2
3
4
5
+
3
V
3
BM0
3
B-
S
R
SS
-TBT
1FT
3
9FT0
10K
3
FT0
+
3
V
3
MI
S
C
A7
1
1
D
A
0
1
E
A
14
7
0
1
2
6
16
7F10-1
3
BCM7206
1
3
4
5
15
2
1
3
1
9
8
11
Φ
R
S
2
3
2
S
T
3
2
3
2C
7FT1
FF
S
4
FF
S
2
FF
S3
9
4
1
1
1
7
0
1
2
6
16
3
4
5
15
2
1
3
1
8
Φ
R
S
2
3
2
S
T
3
2
3
2C
7FT0
1
2FT1
100n
3
FT1
10K
10K
3
FT2
1
2
3
4
5
+
3
V
3
BM0
3
B-
S
R
SS
-TBT
1FT5
100n
+
3
V
3
2FT
3
9FT
3
9FT2
1
2
3
4
5
1FT4
BM0
3
B-
S
R
SS
-TBT
2FT7
100n
2FT0
100n
GP-UART-TXD-0
GP-UART-RXD-0
GP-UART-TXD-1
GP-UART-RXD-1
GP-UART-TXD-2
GP-UART-RXD-2
DAA-AOUT
IR-OUT
GP-UART-RXD-0
GP-UART-TXD-0
GP-UART-RXD-1
GP-UART-TXD-1
GP-UART-RXD-2
GP-UART-TXD-2