Circuit Diagrams and PWB Layouts
10.
SSB: Stand-by MCU
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0
1
0
1
1
1
1
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
6
A
1
0
1
4
C
9
C
2
0
1
4
C
6
A
3
0
1
4
C
5
A
4
0
1
4
C
9
B
5
0
1
4
C
0
1
B
6
0
1
4
C
4
F
7
0
1
4
C
0
1
E
8
0
1
4
C
0
1
E
9
0
1
4
C
5
A
1
0
1
4
D
5
A
1
0
1
4
B
F
3
E
3
0
1
4
B
F
3
F
1
0
1
4
Q
7
B
2
0
1
4
Q
2
C
3
0
1
4
Q
2
D
4
0
1
4
Q
5
C
5
0
1
4
Q
5
D
6
0
1
4
Q
2
E
7
0
1
4
Q
5
E
8
0
1
4
Q
2
A
9
0
1
4
Q
2
C
0
1
1
4
Q
3
A
1
0
1
4
R
9
C
2
0
1
4
R
5
A
3
0
1
4
R
3
A
4
0
1
4
R
3
A
5
0
1
4
R
3
A
6
0
1
4
R
3
A
7
0
1
4
R
3
A
8
0
1
4
R
3
A
9
0
1
4
R
4
A
0
1
1
4
R
4
A
1
1
1
4
R
4
A
2
1
1
4
R
4
A
3
1
1
4
R
4
A
4
1
1
4
R
4
A
5
1
1
4
R
4
A
6
1
1
4
R
5
B
7
1
1
4
R
5
B
8
1
1
4
R
5
B
9
1
1
4
R
8
A
0
2
1
4
R
5
B
1
2
1
4
R
8
B
2
2
1
4
R
2
B
3
2
1
4
R
7
B
4
2
1
4
R
2
B
5
2
1
4
R
7
B
6
2
1
4
R
5
B
7
2
1
4
R
5
B
8
2
1
4
R
5
B
9
2
1
4
R
5
B
0
3
1
4
R
2
B
1
3
1
4
R
5
B
2
3
1
4
R
5
B
3
3
1
4
R
5
B
4
3
1
4
R
5
B
5
3
1
4
R
5
C
6
3
1
4
R
2
F
7
3
1
4
R
3
F
8
3
1
4
R
3
F
9
3
1
4
R
7
D
0
4
1
4
R
3
F
1
4
1
4
R
7
F
2
4
1
4
R
7
E
3
4
1
4
R
3
C
5
4
1
4
R
3
D
6
4
1
4
R
5
C
7
4
1
4
R
5
D
8
4
1
4
R
3
E
9
4
1
4
R
5
E
0
5
1
4
R
2
A
1
5
1
4
R
2
C
2
5
1
4
R
3
C
3
5
1
4
R
3
D
4
5
1
4
R
6
C
5
5
1
4
R
6
D
6
5
1
4
R
3
E
7
5
1
4
R
6
E
8
5
1
4
R
8
E
9
5
1
4
R
6
A
1
0
1
4
U
9
C
2
0
1
4
U
4
F
3
0
1
4
U
8
E
4
0
1
4
U
8
E
5
0
1
4
U
9
B
1
0
1
4
X
I
C
S
O
T
W
_
T
E
S
E
R
T
W
_
T
E
S
E
R
O
C
S
O
1
Y
E
K
7
1
,
3
1
7
1
,
3
1
F
F
O
_
N
O
_
C
D
3
1
2
2
2
8
T
M
_
T
S
R
Y
B
D
N
A
T
S
1
2
,
3
1
Y
B
T
S
2
D
E
L
7
1
,
3
1
W
S
_
R
W
P
_
V
5
1
2
,
3
1
3
V
3
_
R
I
_
C
R
7
1
,
3
1
1
D
X
T
6
1
1
D
X
R
6
1
C
N
Y
S
H
_
C
P
4
C
N
Y
S
V
_
C
P
4
L
C
S
_
1
P
S
I
4
A
D
S
_
1
P
S
I
4
C
E
C
_
U
C
M
0
1
L
C
S
_
T
M
3
1
,
9
A
D
S
_
T
M
3
1
,
9
3
1
O
S
_
I
P
S
#
S
C
_
I
P
S
3
1
I
S
_
I
P
S
3
1
A
D
S
6
1
L
C
S
6
1
P
W
_
M
O
R
P
E
E
3
1
W
S
_
R
W
P
_
D
U
A
0
2
,
3
1
3
1
#
S
C
_
I
P
S
3
1
I
S
_
I
P
S
K
C
S
I
P
S
3
1
O
S
_
I
P
S
3
1
#
R
W
_
H
S
A
L
F
3
1
C
N
Y
S
H
_
C
P
4
C
N
Y
S
V
_
C
P
4
3
1
C
N
Y
S
V
_
T
M
3
1
C
N
Y
S
H
_
T
M
T
N
I
_
T
M
3
1
7
1
,
3
1
1
D
X
T
_
T
M
1
D
X
T
6
1
1
D
X
R
_
T
M
7
1
,
3
1
1
D
X
R
6
1
L
C
S
6
1
3
1
,
9
L
C
S
_
T
M
A
D
S
6
1
3
1
,
9
A
D
S
_
T
M
Y
B
T
S
_
3
V
3
+
Y
B
T
S
_
3
V
3
+
Y
B
T
S
_
3
V
3
+
Y
B
T
S
_
3
V
3
+
3
V
3
+
F
_
3
V
3
+
F
_
3
V
3
+
F
_
3
V
3
+
F
_
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
%
5
W
6
1
/
1
R
7
4
9
2
1
4
R
R4106
-5
%
1/16W
2
0
1
4
Q
2
0
0
7
N
2
6
5
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
3
0
1
4
Q
2
0
0
7
N
2
W
6
1
/
1
%
5
-
+
M
H
O
3
3
2
2
1
4
R
8
0
1
4
C
V
0
1
U
0
1
8
0
1
4
Q
2
0
0
7
N
2
9
0
1
4
C
V
6
1
N
0
0
1
R4116
6
K
8
1/16W 5
%
%
5
W
6
1
/
1
R
7
4
5
3
1
4
R
D4101
L
S
414
8
2
5
1
4
R
)
C
N
(
%
5
W
6
1
/
1
K
0
1
5
5
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
%
5
W
6
1
/
1
R
7
4
8
2
1
4
R
R4114
-5
%
1/16W
3
0
1
4
U
T
-
H
S
-
N
C
2
3
C
4
2
T
A
1
2
3
4
5
6
7
8
0
A
1
A
2
A
D
N
G
A
D
S
L
C
S
P
W
C
C
V
0
5
1
4
R
)
C
N
(
M
H
O
0
6
4
1
4
R
)
C
N
(
M
H
O
0
6
0
1
4
C
V
0
5
P
2
2
7
5
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
R4110
-5
%
1/16W
1
0
1
4
X
z
H
K
8
6
7
.
2
3
1
2
)
C
N
(
W
6
1
/
1
5
0
R
0
9
5
1
4
R
4
0
1
4
Q
2
0
0
7
N
2
%
5
W
6
1
/
1
R
7
4
2
3
1
4
R
R4112
33
K OHM 1/16W(NC)
%
5
W
6
1
/
1
R
7
4
7
2
1
4
R
4
5
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
0
2
1
4
R
%
5
W
6
1
/
1
K
3
3
2
4
1
4
R
)
C
N
(
K
0
1
R4105
-5
%
1/16W
R410
3
-5
%
1/16W
%
5
W
6
1
/
1
R
7
4
1
2
1
4
R
1
0
1
4
B
F
A
m
0
0
0
3
/
R
0
2
1
1
2
9
0
1
4
Q
)
C
N
(
2
0
0
7
N
2
7
0
1
4
C
V
6
1
N
0
0
1
3
4
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
3
3
C
C
A
/
5
0
1
4
U
G
2
1
-
I
M
D
5
0
4
6
L
5
2
X
M
1
2
3
4
5
6
7
8
9
0
1
1
1
2
1
3
1
4
1
5
1
6
1
D
L
O
H
C
C
V
C
N
C
N
C
N
C
N
S
C
1
O
I
S
/
O
S
P
W
D
N
G
C
N
C
N
C
N
C
N
0
O
I
S
/
I
S
K
L
C
S
1
0
1
4
C
V
6
1
N
0
0
1
2
0
1
4
R
)
C
N
(
K
0
0
1
4
0
1
4
U
)
C
N
(
G
2
1
-
I
2
M
D
5
0
2
3
L
5
2
X
M
1
2
3
4
8
7
6
5
#
S
C
O
S
#
W
D
N
G
C
C
V
#
D
L
O
H
K
C
S
I
S
3
0
1
4
C
3
V
6
U
0
1
R4115
33
K 1/16W 5
%
8
3
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
8
4
1
4
R
)
C
N
(
M
H
O
0
%
5
W
6
1
/
1
R
2
2
3
3
1
4
R
1
5
1
4
R
)
C
N
(
%
5
W
6
1
/
1
K
0
1
7
4
1
4
R
)
C
N
(
M
H
O
0
3
2
1
4
R
)
C
N
(
%
5
W
6
1
/
1
R
7
4
4
0
1
4
C
3
V
6
7
U
4
9
4
1
4
R
)
C
N
(
M
H
O
0
5
0
1
4
C
V
0
5
P
2
2
R4101
2
7K 1/16W 5
%
2
0
1
4
U
)
C
N
(
L
W
F
1
0
7
1
P
A
1
2
3
D
N
G
T
E
S
E
R
c
c
V
3
5
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
R4107
-5
%
1/16W
7
0
1
4
Q
2
0
0
7
N
2
%
5
W
6
1
/
1
R
7
4
9
1
1
4
R
%
5
W
6
1
/
1
R
2
2
4
3
1
4
R
%
5
W
6
1
/
1
R
7
4
6
3
1
4
R
4
2
1
4
R
%
5
W
6
1
/
1
R
7
4
7
3
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
0
4
1
4
R
%
5
W
0
1
/
1
K
1
5
4
1
4
R
)
C
N
(
M
H
O
0
2
0
1
4
C
)
C
N
(
V
6
1
N
0
0
1
R410
8
10K(NC)
5
0
1
4
Q
2
0
0
7
N
2
6
0
1
4
Q
2
0
0
7
N
2
3
0
1
4
B
F
A
m
0
0
0
3
/
R
0
2
1
1
2
R4109
10K(NC)
%
5
W
6
1
/
1
R
7
4
8
1
1
4
R
R4104
-5
%
1/16W
)
C
N
(
%
5
W
6
1
/
1
R
7
4
1
3
1
4
R
9
3
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
R4111
-5
%
1/16W
%
5
W
6
1
/
1
R
7
4
0
3
1
4
R
5
2
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
0
0
1
R411
3
-5
%
1/16W
1
0
1
4
U
T
W
0
4
2
G
S
-
F
3
0
7
6
T
W
2
1
2
2
1
2
0
2
9
1
6
5
24
9
8
1
7
1
8
0
1
2
3
3
2
1
1
1
7
4
3
1
4
1
6
1
5
1
I
C
S
O
K
2
3
O
C
S
O
K
2
3
0
D
A
/
0
A
O
I
P
G
1
D
A
/
1
A
O
I
P
G
2
D
A
/
2
A
O
I
P
G
R
I
/
3
D
A
/
3
A
O
I
P
G
0
M
W
P
/
0
C
O
I
P
G
1
M
W
P
/
1
C
O
I
P
G
VDD_RTC
N
I
H
/
5
B
O
I
P
G
3
L
C
S
/
4
A
O
I
P
G
3
A
D
S
/
5
A
O
I
P
G
D
X
T
/
2
Q
R
I
/
6
B
O
I
P
G
N
I
V
/
4
B
O
I
P
G
VDD
V
SS
0
Q
R
I
/
2
B
O
I
P
G
1
Q
R
I
/
3
B
O
I
P
G
D
X
R
/
3
Q
R
I
/
7
B
O
I
P
G
T
S
P
N
2
A
D
S
/
1
B
O
I
P
G
2
L
C
S
/
0
B
O
I
P
G
1
L
C
S
/
6
A
O
I
P
G
1
A
D
S
/
7
A
O
I
P
G
%
5
W
6
1
/
1
R
7
4
7
1
1
4
R
0
1
1
4
Q
)
C
N
(
2
0
0
7
N
2
1
4
1
4
R
%
5
W
6
1
/
1
R
7
4
8
5
1
4
R
W
6
1
/
1
%
5
-
+
M
H
O
K
0
1
)
C
N
(
R
7
4
6
2
1
4
R
1
0
1
4
Q
G
I
T
1
1
2
2
N
U
M
B09
B09
1
8
400_525_090
3
01.ep
s
090619
S
t
a
nd-
b
y MCU