IC Data Sheets
8.
8.2
Diagram
B04, STA381BWTR (IC U6001)
Figure 8-4 Internal block diagram and pin configuration
19240_
3
00_120221.ep
s
Block dia
g
ram
Pinnin
g
information
1
2
3
4
5
6
7
8
9
10
11
12
3
6
3
5
3
4
33
3
2
3
1
3
0
29
2
8
27
26
25
VCC_REG
V
SS
_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
VDD_REG
GND_REG
MCLK
AGNDPLL
VREGFILT
TWARNEXT/FFX4B
EAPD/FFX4A
FFX
3
B
FFX
3
A
GNDDIG1
VDDDIG1
VDD
3
V
3
CHP
CPP
GNDP
S
UB
1
3
14
15
16
17
1
8
19
20
21
22
2
3
24
4
8
47
46
45
44
4
3
42
41
40
3
9
38
3
7
F
3
X
_FI
LT
F
3
XL
F
3
XR
LIN
E
INL
LIN
E
INR
LIN
E
HPOUT_L
LIN
E
HPOUT_R
GND
A
S
OFTM
UTE
VDD
3
V
3
CPV
SS
CPM
VDD
D
IG2
GNDDIG2
TE
S
TMODE
S
A
S
CL
S
DA
INTLINE
PWDN
RE
S
ET
S
DI
LRCKI
BICK
I
S
TA
38
1BW
PWDN
TE
S
TMODE
LRCKI
BICKI
4
H
a
lf
Bridge
s
OUT 1A
OUT 1B
OUT 2A
OUT 2B
FFX
3
A
FFX
3
B
MCLK
S
DI
LINEINL
LINEINR
LINEHPOUT_L
LINEHPOUT_R
S
DA
S
CL
IIC
CPV
SS
CPP
FFX4A
FFX4B
GND
_REG
S
OFT_MUTE
2
x
GND
2 x
V
C
C
VDD_REG
GNDP
S
UB
2 x
VDD
D
IG
2 x
GNDDIG
VREGFIL
T
AGNDPLL
VCC_REG
V
SS
_R
EG
CPM
2.1 Ch
a
nnel
A
u
dio Proce
ss
or
S
TA
u
dioFx
TM
S
T
S
pe
a
ker
Sa
fe
TM
P
a
r
a
metric EQ
Vol
u
me
B
ass
a
nd Tre
b
le
S
pe
a
ker Compen
sa
tion
S
tereo Widening
S
A
RE
S
ET
INTLINE
GND
A
He
a
dph one
(2Vrm
s
)
PLL
Neg
a
tive
Ch
a
rge
P
u
mp
-
3
.
3
V
Control logic
&
Protection
s
REG_M
3
VDD
3
V
3
CHP
F
3
X_FILT
FFX
TM
Mod
u
l
a
tor
Bin
a
ry
Tern
a
ry
F
3
XL
F
3
XR
S
TA
38
1BW