Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 62
SHA2.0U LA
9.
9.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Index of this chapter:
9.1 Introduction
9.2 Block Diagram
9.3 Input/Output
9.4 Abbreviation List
9.5 IC Data Sheets
and an integrated output display interface that can support
TTL output or LVDS interface. It supports de-interlaced full-
screen video, split screen, frame rate conversion, and aspect
ratio conversion for various video sources. To further reduce
system costs, the MST61510A also integrates intelligent power
management control capability for green-mode requirements
and spread-spectrum support for EMI management.
The
MSP3420G
of single-chip Multistandard Sound Processors
covers the sound processing of all analog TV-Standards world-
wide, as well as the NICAM digital sound standards. The full TV
sound processing, starting with analog sound IF signal-in, down
to processed analog AF-out, is performed on a single chip.
This new generation of TV sound processing ICs now includes
versions for processing the multichannel television sound (MTS)
signal conforming to the standard recommended by the Broadcast
Television Systems Committee (BTSC). The DBX noise reduction,
or alternatively, Micronas Noise Reduction (MNR) is performed
alignment free. This chip has the following features:
•
Analog RGB/YPbPr Input Ports
•
DVI/HDCP Compliant Input Port
•
Video Input Port
•
Auto-Configuration/Auto-Detection
•
High-Performance Scaling Engine
•
Video Processing & Conversion
On-Screen OSD Controller
Output Display Interface
External Connection/Component
9.1
Introduction
•
All analog FM-Stereo A2 and satellite standards
•
Simultaneous demodulation of (very) high-deviation FM-Mono
and NICAM
•
Adaptive deemphasis for satellite (Wegener-Panda, acc. to
ASTRA specification)
•
ASTRA Digital Radio (ADR) together with DRP3510A
•
All NICAM standards
•
Alignment free digital DBX noise reduction for BTSC Stereo
and SAP
•
•
•
TVP5147
is a high quality, single-chip digital video decoder
that digitizes and decodes all popular base-band analog video
formats into digital component video. TVP5147 supports the
A/D conversion of component YPbPr signals, as well as the
A/D conversion and decoding of NTSC, PAL and SECAM
composite and S-Video into component YCbCr. This chip
includes two 10-bit 30-MSPS A/D converters. Prior to each
A/D converter, each analog channel contains an analog circuit,
which clamps the input to a reference voltage and applies a
programmable gain and offset. A total of 10 video input
terminals can be configured to any combination of YPbPr,
CVBS, S-Video video inputs. This chip has the following
features:
•
Two 30-MSPS, 10-bit A/D Channels with programmable
gain control
•
Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N,
Nc, 60) and SECAM (B, D, G, K, K1, L) CVBS, S-video
•
Supports analog component YPbPr video formats with
embedded sync
•
Ten analog video input terminals for multi-source
connection
•
Support analog video output
•
User-programmable video output formats
HSYNC/VSYNC outputs with programmable position,
polarity and width and FID (Field ID) output
Composite and S-Video processing
Vertical Blank Interval Data Processor
I
2
C host port interface
Reduced power consumption: 1.8V digital core, 3.3V for
digital IO and 1.8V/3.3 analog core with power-save and
power-down modes
•
•
•
•
•
The
MST61510A
is a high performance and fully integrated
graphics processing IC solution for multi-function LCD monitor
/TV with resolutions up to SXGA. It is configured with an
integrated triple-ADC/PLL, an integrated DVI/HDCP receiver,
a video de-interlacer, a high quality scaling engine, an
on-screen display controller, a built-in output clock generator
The
MM502
micro-controller is an 8051 CPU core embedded
device targeted for LCD Monitor, LCD TV or smart panel
applications. It includes an 8051 CPU core, 1024-byte SRAM,
14 PWM DACs, VESA DDC for both D-sub and DVI interfaces,
4-channel 8-bit ADC, hardware ISP without boot code and a
128K-byte internal program Flash-ROM in 44-pin PLCC
package.
•
8051 core, 12MHz operating frequency with double CPU
clock option
•
3.3V/5V power supply; 5V I/O tolerant
•
1024-byte RAM; 128K-byte program Flash-ROM support
In System Programming (ISP) without boot code
•
Maximum 14 channels of PWM DAC
•
Maximum 38 (44-pin) or 36 (42-pin) I/O pins
•
SYNC processor for composite separation/insertion, H/V
polarity/frequency check and polarity adjustment
Clock output to drive other devices
Built-in low power reset circuit
Compliant with VESA DDC1/2B/2Bi/2B+ standard
Triple slave IIC addresses; two H/W auto transfer DDC1/
DDC2x data for both D-sub and DVI interfaces
Single master IIC interface for internal device
communication
Maximum 4-channel 8-bit A/D converter
Flash-ROM program code protection selection
•
•
•
•
•
•
•
