1-9-7
Digital Signal Process Block Diagram
T8201BLD
C1
6
D1
8
A1
7
B1
5
D
VD-LD
8
CD-LD
10
PD-MONI
7
FS(+)
2
FS(-)
3
TS(+)
1
TS(-)
4
CN201
CN201
CN201
IC201
(SW)
IC101
(MICR
O CONTR
OLLER)
FS
FS(+)
CD/D
VD
FS(-)
TS(+)
TS(-)
TS
DETECT
OR
CD/D
VD
19
Q251,Q252
CD
D
V
D
AMP
Q253,Q254
AMP
4
1
3
6
GND(D
VD-PD)
6
GND(CD-PD)
5
GND(LD)
9
RF
SIGNAL
PR
OCESS
CIRCUIT
D
VD/CD
FORMA
TTER
A
UDIO
I/F
VIDEO
I/F
NTSC/P
AL
ENCODER
DMA
BCU
INST
.
RO
M
32BIT
CPU
D
ATA
RAM
INTERR
UPT
CONTR
OLLER
W
A
TCH DOG
TIMER
CPU
I/F
TIMER
DECODER
I/F
CPU
I/F
READ
MEMOR
Y
D
ATA
RAM
DSP
DECODER
I/O
PR
OCESSOR
INST
.
RO
M
D
ATA
RAM
INST
.
RO
M
SERIAL
GENERAL
I/O
INTERR
UPT
CONTR
OLLER
TIMER
W
A
TCH DOG
TIMER
REMO
TE
CONTR
OL
32BIT CPU
STREAM
I/F
EXTERNAL
MEMOR
Y
I/F
SDRAM
ECC
UMA
C
100
115
116
113
114
106
104
105
103
62
DEB
UG
BCU
INST
CA
CHE
D
ATA
CA
CHE
151
146
144
SDRAM ADDRESS(0-10)
IC103
(FLASH R
OM)
FLASH
RO
M
29
36
38
45
~
~
D
VD VIDEO
SIGNAL
FDQ (0-15)
~
1
9
16
25
48
~
F
ADR (0-19)
SDRAM D
A
T
A(0-15)
PICK-UP
UNIT
T
O
D
V
D SYSTEM
CONTR
O
L/SER
V
O
BLOCK DIA
GRAM
D
VD MAIN CB
A UNIT
IC501
(SDRAM)
SDRAM D
A
T
A(0-15)
SDRAM ADDRESS(0-10)
194
209
~
2
12
39
49
~
~
20
24
27
32
~
~
159
178
~
99
98
97
21~30
34~42
212
1~4
7~14
17~18
215~216
A
UDIO D/A
CONVER
TER
131
D/A
D/A
139
Y
C
TO
IF/VIDEO
BLOCK
DIA
GRAM
<TV SECTION>
CN002
CN2
8
D
VD-Y
6
D
VD-C
CN2
T
O
A
UDIO
BLOCK DIA
GRAM
<TV SECTION>
CN002
4
D
VD-A
UDIO(L)
3
D
VD-A
UDIO(R)
9
D
VD-A
UDIO-MUTE
D
VD A
UDIO SIGNAL
“
“ = SMD
NO
TE FOR
WIRE CONNECT
ORS:
1.
PREFIX SYMBOL "CN" MEANS CONNECT
OR.
(CAN DISCONNECT AND RECONNECT
.)
2.
PREFIX SYMBOL "CL" MEANS
WIRE-SOLDER
HOLES OF
THE PCB
.
(WIRE IS SOLDERED DIRECTL
Y
.)
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Summary of Contents for 13MC3206/37
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